24cd7ecb38
Convert layerscape PCIe bind document to the preferred YAML format. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/20240207231550.2663689-1-Frank.Li@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
103 lines
2.4 KiB
YAML
103 lines
2.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Layerscape PCIe Endpoint(EP) controller
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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description:
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This PCIe EP controller is based on the Synopsys DesignWare PCIe IP.
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This controller derives its clocks from the Reset Configuration Word (RCW)
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which is used to describe the PLL settings at the time of chip-reset.
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Also as per the available Reference Manuals, there is no specific 'version'
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register available in the Freescale PCIe controller register set,
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which can allow determining the underlying DesignWare PCIe controller version
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information.
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properties:
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compatible:
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enum:
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- fsl,ls2088a-pcie-ep
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- fsl,ls1088a-pcie-ep
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- fsl,ls1046a-pcie-ep
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- fsl,ls1028a-pcie-ep
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- fsl,lx2160ar2-pcie-ep
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: regs
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- const: addr_space
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fsl,pcie-scfg:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: A phandle to the SCFG device node. The second entry is the
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physical PCIe controller index starting from '0'. This is used to get
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SCFG PEXN registers.
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big-endian:
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$ref: /schemas/types.yaml#/definitions/flag
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description: If the PEX_LUT and PF register block is in big-endian, specify
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this property.
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dma-coherent: true
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interrupts:
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minItems: 1
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maxItems: 2
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interrupt-names:
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minItems: 1
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maxItems: 2
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required:
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- compatible
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- reg
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- reg-names
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allOf:
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- if:
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properties:
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compatible:
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enum:
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- fsl,ls1028a-pcie-ep
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- fsl,ls1046a-pcie-ep
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- fsl,ls1088a-pcie-ep
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then:
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properties:
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interrupt-names:
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items:
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- const: pme
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie_ep1: pcie-ep@3400000 {
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compatible = "fsl,ls1028a-pcie-ep";
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reg = <0x00 0x03400000 0x0 0x00100000
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0x80 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
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interrupt-names = "pme";
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num-ib-windows = <6>;
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num-ob-windows = <8>;
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status = "disabled";
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};
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};
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...
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