320e10986e
Now that its contents were converted to a DT schema, replace the references for the old file on existing properties. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/dfff4d94631546c53450d1baeddc694dd26b5c36.1626608375.git.mchehab+huawei@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
51 lines
1.9 KiB
Plaintext
51 lines
1.9 KiB
Plaintext
* Axis ARTPEC-6 PCIe interface
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in snps,dw-pcie.yaml.
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Required properties:
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- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
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"axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
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"axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
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"axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
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- reg: base addresses and lengths of the PCIe controller (DBI),
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the PHY controller, and configuration address space.
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- reg-names: Must include the following entries:
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- "dbi"
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- "phy"
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- "config"
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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- "msi": The interrupt that is asserted when an MSI is received
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- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
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used to enable and control the Synopsys IP.
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Example:
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pcie@f8050000 {
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compatible = "axis,artpec6-pcie", "snps,dw-pcie";
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reg = <0xf8050000 0x2000
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0xf8040000 0x1000
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0xc0000000 0x2000>;
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reg-names = "dbi", "phy", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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/* downstream I/O */
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ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
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/* non-prefetchable memory */
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0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
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num-lanes = <2>;
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bus-range = <0x00 0xff>;
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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axis,syscon-pcie = <&syscon>;
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};
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