5db62b7d3c
dtschema package with core schemas deprecated pci-bus.yaml schema in favor of pci-host-bridge.yaml. Update all bindings to use the latter one. The difference between pci-bus.yaml and pci-host-bridge.yaml is only in lack of "reg" property defined by the latter, which should not have any effect here, because all these bindings define the "reg". The change is therefore quite trivial, however it requires dtschema package v2024.02 or newer. Link: https://lore.kernel.org/linux-pci/20240413151617.35630-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # Renesas Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
135 lines
2.9 KiB
YAML
135 lines
2.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic Meson AXG DWC PCIe SoC controller
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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description:
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Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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- $ref: /schemas/pci/snps,dw-pcie-common.yaml#
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# We need a select here so we don't match all nodes with 'snps,dw-pcie'
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select:
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properties:
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compatible:
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enum:
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- amlogic,axg-pcie
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- amlogic,g12a-pcie
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- amlogic,axg-pcie
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- amlogic,g12a-pcie
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- const: snps,dw-pcie
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reg:
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items:
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- description: External local bus interface registers
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- description: Meson designed configuration registers
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- description: PCIe configuration space
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reg-names:
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items:
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- const: elbi
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- const: cfg
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- const: config
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: PCIe GEN 100M PLL clock
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- description: PCIe RC clock gate
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- description: PCIe PHY clock
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clock-names:
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items:
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- const: pclk
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- const: port
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- const: general
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phys:
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maxItems: 1
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phy-names:
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const: pcie
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resets:
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items:
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- description: Port Reset
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- description: Shared APB reset
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reset-names:
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items:
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- const: port
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- const: apb
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num-lanes:
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const: 1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- clock
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- clock-names
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- "#address-cells"
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- "#size-cells"
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- "#interrupt-cells"
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- interrupt-map
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- interrupt-map-mask
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- ranges
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- bus-range
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- device_type
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- num-lanes
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- phys
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- phy-names
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie: pcie@f9800000 {
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compatible = "amlogic,axg-pcie", "snps,dw-pcie";
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reg = <0xf9800000 0x400000>, <0xff646000 0x2000>, <0xf9f00000 0x100000>;
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reg-names = "elbi", "cfg", "config";
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interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
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clocks = <&pclk>, <&clk_port>, <&clk_phy>;
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clock-names = "pclk", "port", "general";
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resets = <&reset_pcie_port>, <&reset_pcie_apb>;
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reset-names = "port", "apb";
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phys = <&pcie_phy>;
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phy-names = "pcie";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
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bus-range = <0x0 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <1>;
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ranges = <0x82000000 0 0 0xf9c00000 0 0x00300000>;
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};
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...
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