51a0f37088
Convert the device tree bindings for the MISC register block found on NVIDIA Tegra SoCs from plain text to json-schema format. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
52 lines
1.3 KiB
YAML
52 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra APBMISC block
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- nvidia,tegra210-apbmisc
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- nvidia,tegra124-apbmisc
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- nvidia,tegra114-apbmisc
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- nvidia,tegra30-apbmisc
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- const: nvidia,tegra20-apbmisc
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- items:
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- const: nvidia,tegra20-apbmisc
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reg:
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items:
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- description: physical address and length of the registers which
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contain revision and debug features
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- description: physical address and length of the registers which
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indicate strapping options
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nvidia,long-ram-code:
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description: If present, the RAM code is long (4 bit). If not, short
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(2 bit).
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type: boolean
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additionalProperties: false
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required:
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- compatible
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- reg
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examples:
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- |
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apbmisc@70000800 {
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compatible = "nvidia,tegra20-apbmisc";
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reg = <0x70000800 0x64>, /* Chip revision */
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<0x70000008 0x04>; /* Strapping options */
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};
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