51a0f37088
Convert the device tree bindings for the MISC register block found on NVIDIA Tegra SoCs from plain text to json-schema format. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
44 lines
1.1 KiB
YAML
44 lines
1.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra186 (and later) MISC register block
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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description: The MISC register block found on Tegra186 and later SoCs contains
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registers that can be used to identify a given chip and various strapping
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options.
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properties:
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compatible:
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enum:
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- nvidia,tegra186-misc
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- nvidia,tegra194-misc
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- nvidia,tegra234-misc
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reg:
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items:
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- description: physical address and length of the registers which
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contain revision and debug features
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- description: physical address and length of the registers which
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indicate strapping options
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additionalProperties: false
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required:
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- compatible
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- reg
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examples:
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- |
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misc@100000 {
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compatible = "nvidia,tegra186-misc";
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reg = <0x00100000 0xf000>,
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<0x0010f000 0x1000>;
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};
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