e1cbc3b96a
Including:
- Intel VT-d driver updates
- Domain force snooping improvement.
- Cleanups, no intentional functional changes.
- ARM SMMU driver updates
- Add new Qualcomm device-tree compatible strings
- Add new Nvidia device-tree compatible string for Tegra234
- Fix UAF in SMMUv3 shared virtual addressing code
- Force identity-mapped domains for users of ye olde SMMU
legacy binding
- Minor cleanups
- Patches to fix a BUG_ON in the vfio_iommu_group_notifier
- Groundwork for upcoming iommufd framework
- Introduction of DMA ownership so that an entire IOMMU group
is either controlled by the kernel or by user-space
- MT8195 and MT8186 support in the Mediatek IOMMU driver
- Patches to make forcing of cache-coherent DMA more coherent
between IOMMU drivers
- Fixes for thunderbolt device DMA protection
- Various smaller fixes and cleanups
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAmKWCbUACgkQK/BELZcB
GuPHmRAAuoH9iK/jrC3SgrqpBfH2iRN7ovIX8dFvgbQWX27lhXF4gvj2/nYdIvPK
75j/LmdibuzV3Iez4kjbGKNG1AikwK3dKIH21a84f3ctnoamQyL6nMfCVBFaVD/D
kvPpTHyjbGPNf6KZyWQdkJ5DXD1aoG1DKkBnslH5pTNPqGuNqbcnRTg0YxiJFLBv
5w2B6jL06XRzunh+Sp1Dbj+po8ROjLRCEU+tdrndO8W/Dyp6+ZNNuxL9/3BM9zMj
py0M4piFtGnhmJSdym1eeHm7r1YRjkZw+MN+e8NcrcSihmDutEWo7nRRxA5uVaa+
3O2DNERqCvQUYxfNRUOKwzV8v51GYQHEPhvOe/MLgaEQDmDmlF2dHNGm93eCMdrv
m1cT011oU7pa4qHomwLyTJxSsR7FzJ37igq/WeY++MBhl+frqfzEQPVxF+W7GLb8
QvT/+woCPzLVpJbE7s0FUD4nbPd8c1dAz4+HO1DajxILIOTq1bnPIorSjgXODRjq
yzsiP1rAg0L0PsL7pXn3cPMzNCE//xtOsRsAGmaVv6wBoMLyWVFCU/wjPEdjrSWA
nXpAuCL84uxCEl/KLYMsg9UhjT6ko7CuKdsybIG9zNIiUau43uSqgTen0xCpYt0i
m//O/X3tPyxmoLKRW+XVehGOrBZW+qrQny6hk/Zex+6UJQqVMTA=
=W0hj
-----END PGP SIGNATURE-----
Merge tag 'iommu-updates-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates from Joerg Roedel:
- Intel VT-d driver updates:
- Domain force snooping improvement.
- Cleanups, no intentional functional changes.
- ARM SMMU driver updates:
- Add new Qualcomm device-tree compatible strings
- Add new Nvidia device-tree compatible string for Tegra234
- Fix UAF in SMMUv3 shared virtual addressing code
- Force identity-mapped domains for users of ye olde SMMU legacy
binding
- Minor cleanups
- Fix a BUG_ON in the vfio_iommu_group_notifier:
- Groundwork for upcoming iommufd framework
- Introduction of DMA ownership so that an entire IOMMU group is
either controlled by the kernel or by user-space
- MT8195 and MT8186 support in the Mediatek IOMMU driver
- Make forcing of cache-coherent DMA more coherent between IOMMU
drivers
- Fixes for thunderbolt device DMA protection
- Various smaller fixes and cleanups
* tag 'iommu-updates-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (88 commits)
iommu/amd: Increase timeout waiting for GA log enablement
iommu/s390: Tolerate repeat attach_dev calls
iommu/vt-d: Remove hard coding PGSNP bit in PASID entries
iommu/vt-d: Remove domain_update_iommu_snooping()
iommu/vt-d: Check domain force_snooping against attached devices
iommu/vt-d: Block force-snoop domain attaching if no SC support
iommu/vt-d: Size Page Request Queue to avoid overflow condition
iommu/vt-d: Fold dmar_insert_one_dev_info() into its caller
iommu/vt-d: Change return type of dmar_insert_one_dev_info()
iommu/vt-d: Remove unneeded validity check on dev
iommu/dma: Explicitly sort PCI DMA windows
iommu/dma: Fix iova map result check bug
iommu/mediatek: Fix NULL pointer dereference when printing dev_name
iommu: iommu_group_claim_dma_owner() must always assign a domain
iommu/arm-smmu: Force identity domains for legacy binding
iommu/arm-smmu: Support Tegra234 SMMU
dt-bindings: arm-smmu: Add compatible for Tegra234 SOC
dt-bindings: arm-smmu: Document nvidia,memory-controller property
iommu/arm-smmu-qcom: Add SC8280XP support
dt-bindings: arm-smmu: Add compatible for Qualcomm SC8280XP
...
100 lines
2.8 KiB
YAML
100 lines
2.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/iommu/samsung,sysmmu.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
|
|
|
|
maintainers:
|
|
- Marek Szyprowski <m.szyprowski@samsung.com>
|
|
|
|
description: |+
|
|
Samsung's Exynos architecture contains System MMUs that enables scattered
|
|
physical memory chunks visible as a contiguous region to DMA-capable peripheral
|
|
devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
|
|
|
|
System MMU is an IOMMU and supports identical translation table format to
|
|
ARMv7 translation tables with minimum set of page properties including access
|
|
permissions, shareability and security protection. In addition, System MMU has
|
|
another capabilities like L2 TLB or block-fetch buffers to minimize translation
|
|
latency.
|
|
|
|
System MMUs are in many to one relation with peripheral devices, i.e. single
|
|
peripheral device might have multiple System MMUs (usually one for each bus
|
|
master), but one System MMU can handle transactions from only one peripheral
|
|
device. The relation between a System MMU and the peripheral device needs to be
|
|
defined in device node of the peripheral device.
|
|
|
|
MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System
|
|
MMUs.
|
|
* MFC has one System MMU on its left and right bus.
|
|
* FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
|
|
for window 1, 2 and 3.
|
|
* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
|
|
the other System MMU on the write channel.
|
|
|
|
For information on assigning System MMU controller to its peripheral devices,
|
|
see generic IOMMU bindings.
|
|
|
|
properties:
|
|
compatible:
|
|
const: samsung,exynos-sysmmu
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
minItems: 1
|
|
maxItems: 2
|
|
|
|
clock-names:
|
|
oneOf:
|
|
- items:
|
|
- const: sysmmu
|
|
- items:
|
|
- const: sysmmu
|
|
- const: master
|
|
- items:
|
|
- const: aclk
|
|
- const: pclk
|
|
|
|
"#iommu-cells":
|
|
const: 0
|
|
|
|
power-domains:
|
|
description: |
|
|
Required if the System MMU is needed to gate its power.
|
|
Please refer to the following document:
|
|
Documentation/devicetree/bindings/power/pd-samsung.yaml
|
|
maxItems: 1
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- interrupts
|
|
- clocks
|
|
- clock-names
|
|
- "#iommu-cells"
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/clock/exynos5250.h>
|
|
|
|
sysmmu_gsc0: iommu@13e80000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x13E80000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <2 0>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_GSCL0>,
|
|
<&clock CLK_GSCL0>;
|
|
power-domains = <&pd_gsc>;
|
|
#iommu-cells = <0>;
|
|
};
|