54a75d8f14
The "apps_smmu" on the Qualcomm sdm845 platform is an implementation of the SMMU-500, that consists of a single TCU (Translation Control Unit) and multiple TBUs (Translation Buffer Units). These TBUs have hardware debugging features that are specific and only present on Qualcomm hardware. Represent them as independent DT nodes. List all the resources that are needed to operate them (such as registers, clocks, power domains and interconnects). Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Georgi Djakov <quic_c_gdjako@quicinc.com> Link: https://lore.kernel.org/r/20240417133731.2055383-2-quic_c_gdjako@quicinc.com Signed-off-by: Will Deacon <will@kernel.org>
70 lines
1.8 KiB
YAML
70 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iommu/qcom,tbu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm TBU (Translation Buffer Unit)
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maintainers:
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- Georgi Djakov <quic_c_gdjako@quicinc.com>
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description:
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The Qualcomm SMMU500 implementation consists of TCU and TBU. The TBU contains
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a Translation Lookaside Buffer (TLB) that caches page tables. TBUs provides
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debug features to trace and trigger debug transactions. There are multiple TBU
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instances with each client core.
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properties:
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compatible:
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enum:
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- qcom,sc7280-tbu
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- qcom,sdm845-tbu
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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interconnects:
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maxItems: 1
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power-domains:
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maxItems: 1
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qcom,stream-id-range:
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description: |
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Phandle of a SMMU device and Stream ID range (address and size) that
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is assigned by the TBU
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle of a smmu node
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- description: stream id base address
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- description: stream id size
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required:
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- compatible
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- reg
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- qcom,stream-id-range
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,sdm845.h>
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tbu@150e1000 {
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compatible = "qcom,sdm845-tbu";
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reg = <0x150e1000 0x1000>;
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clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
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interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
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&config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
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power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>;
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qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
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};
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...
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