0dec2d0c8a
Properties with variable number of items per each device are expected to have widest constraints in top-level "properties:" block and further customized (narrowed) in "if:then:". Add missing top-level constraints for clocks and clock-output-names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240818173014.122073-3-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
246 lines
5.5 KiB
YAML
246 lines
5.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas Clock Pulse Generator (CPG)
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description:
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The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
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includes PLLs, and fixed and variable ratio dividers.
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The CPG may also provide a Clock Domain for SoC devices, in combination with
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the CPG Module Stop (MSTP) Clocks.
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properties:
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compatible:
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oneOf:
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- const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
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- const: renesas,r8a7740-cpg-clocks # R-Mobile A1
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- const: renesas,r8a7778-cpg-clocks # R-Car M1
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- const: renesas,r8a7779-cpg-clocks # R-Car H1
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- items:
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- enum:
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- renesas,r7s72100-cpg-clocks # RZ/A1H
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- const: renesas,rz-cpg-clocks # RZ/A1
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- const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 3
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'#clock-cells':
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const: 1
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clock-output-names:
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minItems: 3
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maxItems: 17
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renesas,mode:
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description: Board-specific settings of the MD_CK* bits on R-Mobile A1
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 7
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'#power-domain-cells':
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- clock-output-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r8a73a4-cpg-clocks
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then:
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properties:
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clocks:
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items:
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- description: extal1
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- description: extal2
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clock-output-names:
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items:
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- const: main
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- const: pll0
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- const: pll1
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- const: pll2
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- const: pll2s
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- const: pll2h
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- const: z
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- const: z2
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- const: i
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- const: m3
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- const: b
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- const: m1
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- const: m2
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- const: zx
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- const: zs
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- const: hp
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r8a7740-cpg-clocks
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then:
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properties:
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clocks:
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items:
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- description: extal1
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- description: extal2
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- description: extalr
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clock-output-names:
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items:
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- const: system
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- const: pllc0
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- const: pllc1
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- const: pllc2
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- const: r
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- const: usb24s
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- const: i
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- const: zg
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- const: b
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- const: m1
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- const: hp
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- const: hpp
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- const: usbp
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- const: s
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- const: zb
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- const: m3
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- const: cp
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required:
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- renesas,mode
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r8a7778-cpg-clocks
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then:
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properties:
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clocks:
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maxItems: 1
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clock-output-names:
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items:
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- const: plla
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- const: pllb
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- const: b
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- const: out
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- const: p
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- const: s
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- const: s1
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r8a7779-cpg-clocks
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then:
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properties:
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clocks:
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maxItems: 1
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clock-output-names:
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items:
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- const: plla
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- const: z
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- const: zs
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- const: s
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- const: s1
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- const: p
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- const: b
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- const: out
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r7s72100-cpg-clocks
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then:
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properties:
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clocks:
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items:
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- description: extal1
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- description: usb_x1
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clock-output-names:
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items:
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- const: pll
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- const: i
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- const: g
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- if:
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properties:
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compatible:
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contains:
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const: renesas,sh73a0-cpg-clocks
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then:
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properties:
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clocks:
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items:
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- description: extal1
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- description: extal2
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clock-output-names:
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items:
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- const: main
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- const: pll0
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- const: pll1
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- const: pll2
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- const: pll3
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- const: dsi0phy
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- const: dsi1phy
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- const: zg
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- const: m3
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- const: b
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- const: m1
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- const: m2
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- const: z
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- const: zx
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- const: hp
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- if:
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properties:
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compatible:
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contains:
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enum:
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- renesas,r8a7778-cpg-clocks
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- renesas,r8a7779-cpg-clocks
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- renesas,rz-cpg-clocks
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then:
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required:
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r8a7740-clock.h>
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7740-cpg-clocks";
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reg = <0xe6150000 0x10000>;
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clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
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#clock-cells = <1>;
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clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
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"usb24s", "i", "zg", "b", "m1", "hp", "hpp",
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"usbp", "s", "zb", "m3", "cp";
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renesas,mode = <0x05>;
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};
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