0710c3d304
Use my @kernel.org address everywhere. Signed-off-by: Konrad Dybcio <konradybcio@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240726-topic-konrad_email-v1-3-f94665da2919@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
55 lines
1.3 KiB
YAML
55 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm6375-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller on SM6375
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maintainers:
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- Konrad Dybcio <konradybcio@kernel.org>
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description: |
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Qualcomm display clock control module provides the clocks, resets and power
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domains on SM6375.
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See also:: include/dt-bindings/clock/qcom,dispcc-sm6375.h
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allOf:
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- $ref: qcom,gcc.yaml#
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properties:
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compatible:
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const: qcom,sm6375-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 source from GCC
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- description: Byte clock from DSI PHY
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- description: Pixel clock from DSI PHY
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required:
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- compatible
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,sm6375-gcc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@5f00000 {
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compatible = "qcom,sm6375-dispcc";
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reg = <0x05f00000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_DISP_GPLL0_CLK_SRC>,
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<&dsi_phy 0>,
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<&dsi_phy 1>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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