5576b6f8e9
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-5-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
124 lines
3.4 KiB
YAML
124 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Qualcomm Display Clock & Reset Controller on SM8150/SM8250/SM8350
|
|
|
|
maintainers:
|
|
- Jonathan Marek <jonathan@marek.ca>
|
|
|
|
description: |
|
|
Qualcomm display clock control module provides the clocks, resets and power
|
|
domains on SM8150/SM8250/SM8350.
|
|
|
|
See also::
|
|
include/dt-bindings/clock/qcom,dispcc-sm8150.h
|
|
include/dt-bindings/clock/qcom,dispcc-sm8250.h
|
|
include/dt-bindings/clock/qcom,dispcc-sm8350.h
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- qcom,sc8180x-dispcc
|
|
- qcom,sm8150-dispcc
|
|
- qcom,sm8250-dispcc
|
|
- qcom,sm8350-dispcc
|
|
|
|
clocks:
|
|
minItems: 7
|
|
items:
|
|
- description: Board XO source
|
|
- description: Byte clock from DSI PHY0
|
|
- description: Pixel clock from DSI PHY0
|
|
- description: Byte clock from DSI PHY1
|
|
- description: Pixel clock from DSI PHY1
|
|
- description: Link clock from DP PHY
|
|
- description: VCO DIV clock from DP PHY
|
|
- description: Link clock from eDP PHY
|
|
- description: VCO DIV clock from eDP PHY
|
|
- description: Link clock from DP1 PHY
|
|
- description: VCO DIV clock from DP1 PHY
|
|
- description: Link clock from DP2 PHY
|
|
- description: VCO DIV clock from DP2 PHY
|
|
|
|
clock-names:
|
|
minItems: 7
|
|
items:
|
|
- const: bi_tcxo
|
|
- const: dsi0_phy_pll_out_byteclk
|
|
- const: dsi0_phy_pll_out_dsiclk
|
|
- const: dsi1_phy_pll_out_byteclk
|
|
- const: dsi1_phy_pll_out_dsiclk
|
|
- const: dp_phy_pll_link_clk
|
|
- const: dp_phy_pll_vco_div_clk
|
|
- const: edp_phy_pll_link_clk
|
|
- const: edp_phy_pll_vco_div_clk
|
|
- const: dptx1_phy_pll_link_clk
|
|
- const: dptx1_phy_pll_vco_div_clk
|
|
- const: dptx2_phy_pll_link_clk
|
|
- const: dptx2_phy_pll_vco_div_clk
|
|
|
|
power-domains:
|
|
description:
|
|
A phandle and PM domain specifier for the MMCX power domain.
|
|
maxItems: 1
|
|
|
|
required-opps:
|
|
description:
|
|
A phandle to an OPP node describing required MMCX performance point.
|
|
maxItems: 1
|
|
|
|
required:
|
|
- compatible
|
|
- clocks
|
|
- clock-names
|
|
- '#power-domain-cells'
|
|
|
|
allOf:
|
|
- $ref: qcom,gcc.yaml#
|
|
- if:
|
|
not:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
const: qcom,sc8180x-dispcc
|
|
then:
|
|
properties:
|
|
clocks:
|
|
maxItems: 7
|
|
clock-names:
|
|
maxItems: 7
|
|
|
|
unevaluatedProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
|
#include <dt-bindings/power/qcom,rpmhpd.h>
|
|
clock-controller@af00000 {
|
|
compatible = "qcom,sm8250-dispcc";
|
|
reg = <0x0af00000 0x10000>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&dsi0_phy 0>,
|
|
<&dsi0_phy 1>,
|
|
<&dsi1_phy 0>,
|
|
<&dsi1_phy 1>,
|
|
<&dp_phy 0>,
|
|
<&dp_phy 1>;
|
|
clock-names = "bi_tcxo",
|
|
"dsi0_phy_pll_out_byteclk",
|
|
"dsi0_phy_pll_out_dsiclk",
|
|
"dsi1_phy_pll_out_byteclk",
|
|
"dsi1_phy_pll_out_dsiclk",
|
|
"dp_phy_pll_link_clk",
|
|
"dp_phy_pll_vco_div_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
...
|