c6e87b0667
i.MX95 DISPLAY_MASTER_CSR includes registers to control DSI clock settings, clock gating, and pixel link select. Add dt-schema for it. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20240401-imx95-blk-ctl-v6-3-84d4eca1e759@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
65 lines
1.3 KiB
YAML
65 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX95 Display Master Block Control
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maintainers:
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- Peng Fan <peng.fan@nxp.com>
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properties:
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compatible:
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items:
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- const: nxp,imx95-display-master-csr
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- const: syscon
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reg:
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maxItems: 1
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power-domains:
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maxItems: 1
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clocks:
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maxItems: 1
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'#clock-cells':
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const: 1
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description:
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See
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include/dt-bindings/clock/nxp,imx95-clock.h
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mux-controller:
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type: object
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$ref: /schemas/mux/reg-mux.yaml
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required:
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- compatible
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- reg
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- '#clock-cells'
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- mux-controller
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- power-domains
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- clocks
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additionalProperties: false
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examples:
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- |
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syscon@4c410000 {
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compatible = "nxp,imx95-display-master-csr", "syscon";
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reg = <0x4c410000 0x10000>;
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#clock-cells = <1>;
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clocks = <&scmi_clk 62>;
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power-domains = <&scmi_devpd 3>;
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mux: mux-controller {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4 0x00000001>; /* Pixel_link_sel */
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idle-states = <0>;
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};
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};
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...
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