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linux/Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml
Frank Li 0d796569e1 dt-bindings: clock: qoriq-clock: convert to yaml format
Convert qoria-clock DT binding to yaml format. Split to two files
qoriq-clock.yaml and qoriq-clock-legancy.yaml.

Addtional change:
- Remove clock consumer part in example
- Fixed example dts error
- Deprecated legancy node
- fsl,b4420-clockgen and fsl,b4860-clockgen fallback to fsl,b4-clockgen.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240701205809.1978389-1-Frank.Li@nxp.com
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-07-08 11:58:17 -07:00

85 lines
1.8 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Legacy Clock Block on Freescale QorIQ Platforms
maintainers:
- Frank Li <Frank.Li@nxp.com>
description: |
These nodes are deprecated. Kernels should continue to support
device trees with these nodes, but new device trees should not use them.
Most of the bindings are from the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
properties:
compatible:
enum:
- fsl,qoriq-core-pll-1.0
- fsl,qoriq-core-pll-2.0
- fsl,qoriq-core-mux-1.0
- fsl,qoriq-core-mux-2.0
- fsl,qoriq-sysclk-1.0
- fsl,qoriq-sysclk-2.0
- fsl,qoriq-platform-pll-1.0
- fsl,qoriq-platform-pll-2.0
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
clock-output-names:
minItems: 1
maxItems: 8
'#clock-cells':
minimum: 0
maximum: 1
required:
- compatible
- '#clock-cells'
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,qoriq-sysclk-1.0
- fsl,qoriq-sysclk-2.0
then:
properties:
'#clock-cells':
const: 0
- if:
properties:
compatible:
contains:
enum:
- fsl,qoriq-core-pll-1.0
- fsl,qoriq-core-pll-2.0
then:
properties:
'#clock-cells':
const: 1
description: |
* 0 - equal to the PLL frequency
* 1 - equal to the PLL frequency divided by 2
* 2 - equal to the PLL frequency divided by 4