dd3cb467eb
As indicated in link: https://lore.kernel.org/all/20220822204945.GA808626-robh@kernel.org/ DT schema files should not have 'Device Tree Binding' as part of there title: line. Remove this in most .yaml files, so hopefully preventing developers copying it into new .yaml files, and being asked to remove it. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20220825020427.3460650-1-andrew@lunn.ch Signed-off-by: Rob Herring <robh@kernel.org>
109 lines
2.0 KiB
YAML
109 lines
2.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Allwinner A10 AHB Clock
|
|
|
|
maintainers:
|
|
- Chen-Yu Tsai <wens@csie.org>
|
|
- Maxime Ripard <mripard@kernel.org>
|
|
|
|
deprecated: true
|
|
|
|
properties:
|
|
"#clock-cells":
|
|
const: 0
|
|
|
|
compatible:
|
|
enum:
|
|
- allwinner,sun4i-a10-ahb-clk
|
|
- allwinner,sun6i-a31-ahb1-clk
|
|
- allwinner,sun8i-h3-ahb2-clk
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
minItems: 1
|
|
maxItems: 4
|
|
description: >
|
|
The parent order must match the hardware programming order.
|
|
|
|
clock-output-names:
|
|
maxItems: 1
|
|
|
|
required:
|
|
- "#clock-cells"
|
|
- compatible
|
|
- reg
|
|
- clocks
|
|
- clock-output-names
|
|
|
|
additionalProperties: false
|
|
|
|
allOf:
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
const: allwinner,sun4i-a10-ahb-clk
|
|
|
|
then:
|
|
properties:
|
|
clocks:
|
|
maxItems: 1
|
|
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
const: allwinner,sun6i-a31-ahb1-clk
|
|
|
|
then:
|
|
properties:
|
|
clocks:
|
|
maxItems: 4
|
|
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
const: allwinner,sun8i-h3-ahb2-clk
|
|
|
|
then:
|
|
properties:
|
|
clocks:
|
|
maxItems: 2
|
|
|
|
examples:
|
|
- |
|
|
ahb@1c20054 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-ahb-clk";
|
|
reg = <0x01c20054 0x4>;
|
|
clocks = <&axi>;
|
|
clock-output-names = "ahb";
|
|
};
|
|
|
|
- |
|
|
ahb1@1c20054 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun6i-a31-ahb1-clk";
|
|
reg = <0x01c20054 0x4>;
|
|
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
|
|
clock-output-names = "ahb1";
|
|
};
|
|
|
|
- |
|
|
ahb2_clk@1c2005c {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun8i-h3-ahb2-clk";
|
|
reg = <0x01c2005c 0x4>;
|
|
clocks = <&ahb1>, <&pll6d2>;
|
|
clock-output-names = "ahb2";
|
|
};
|
|
|
|
...
|