84fa8f1590
The Coresight TMC component may be behind an IOMMU which is the case for the Arm Juno SoC and some Qualcomm SoCs. Add 'iommus' property to the binding. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220721212718.1980905-2-robh@kernel.org Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
138 lines
3.5 KiB
YAML
138 lines
3.5 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Arm CoreSight Trace Memory Controller
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maintainers:
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- Mathieu Poirier <mathieu.poirier@linaro.org>
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- Mike Leach <mike.leach@linaro.org>
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- Leo Yan <leo.yan@linaro.org>
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- Suzuki K Poulose <suzuki.poulose@arm.com>
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description: |
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CoreSight components are compliant with the ARM CoreSight architecture
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specification and can be connected in various topologies to suit a particular
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SoCs tracing needs. These trace components can generally be classified as
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sinks, links and sources. Trace data produced by one or more sources flows
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through the intermediate links connecting the source to the currently selected
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sink.
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Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace
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FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
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mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
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# Need a custom select here or 'arm,primecell' will match on lots of nodes
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select:
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properties:
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compatible:
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contains:
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const: arm,coresight-tmc
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required:
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- compatible
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allOf:
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- $ref: /schemas/arm/primecell.yaml#
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properties:
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compatible:
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items:
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- const: arm,coresight-tmc
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- const: arm,primecell
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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items:
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- const: apb_pclk
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- const: atclk
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iommus:
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maxItems: 1
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power-domains:
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maxItems: 1
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arm,buffer-size:
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$ref: /schemas/types.yaml#/definitions/uint32
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deprecated: true
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description:
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Size of contiguous buffer space for TMC ETR (embedded trace router). The
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buffer size can be configured dynamically via buffer_size property in
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sysfs instead.
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arm,scatter-gather:
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type: boolean
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description:
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Indicates that the TMC-ETR can safely use the SG mode on this system.
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arm,max-burst-size:
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description:
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The maximum burst size initiated by TMC on the AXI master interface. The
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burst size can be in the range [0..15], the setting supports one data
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transfer per burst up to a maximum of 16 data transfers per burst.
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 15
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in-ports:
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$ref: /schemas/graph.yaml#/properties/ports
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additionalProperties: false
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properties:
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port:
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description: Input connection from the CoreSight Trace bus.
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$ref: /schemas/graph.yaml#/properties/port
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out-ports:
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$ref: /schemas/graph.yaml#/properties/ports
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additionalProperties: false
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properties:
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port:
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description: AXI or ATB Master output connection. Used for ETR
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and ETF configurations.
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$ref: /schemas/graph.yaml#/properties/port
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- in-ports
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unevaluatedProperties: false
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examples:
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- |
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etr@20070000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x20070000 0x1000>;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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etr_in_port: endpoint {
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remote-endpoint = <&replicator2_out_port0>;
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};
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};
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};
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out-ports {
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port {
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etr_out_port: endpoint {
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remote-endpoint = <&catu_in_port>;
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};
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};
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};
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};
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...
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