4538480b27
Correct spelling mistakes in the documentation to improve readability. Signed-off-by: Amit Vadhavana <av2082000@gmail.com> Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Link: https://lore.kernel.org/r/20240817072724.6861-1-av2082000@gmail.com
141 lines
6.3 KiB
ReStructuredText
141 lines
6.3 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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=========================================
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Vector Extension Support for RISC-V Linux
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=========================================
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This document briefly outlines the interface provided to userspace by Linux in
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order to support the use of the RISC-V Vector Extension.
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1. prctl() Interface
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---------------------
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Two new prctl() calls are added to allow programs to manage the enablement
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status for the use of Vector in userspace. The intended usage guideline for
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these interfaces is to give init systems a way to modify the availability of V
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for processes running under its domain. Calling these interfaces is not
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recommended in libraries routines because libraries should not override policies
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configured from the parent process. Also, users must note that these interfaces
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are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
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to use in a portable code. To get the availability of V in an ELF program,
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please read :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the
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auxiliary vector.
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* prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg)
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Sets the Vector enablement status of the calling thread, where the control
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argument consists of two 2-bit enablement statuses and a bit for inheritance
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mode. Other threads of the calling process are unaffected.
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Enablement status is a tri-state value each occupying 2-bit of space in
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the control argument:
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* :c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default
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enablement status on execve(). The system-wide default setting can be
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controlled via sysctl interface (see sysctl section below).
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* :c:macro:`PR_RISCV_V_VSTATE_CTRL_ON`: Allow Vector to be run for the
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thread.
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* :c:macro:`PR_RISCV_V_VSTATE_CTRL_OFF`: Disallow Vector. Executing Vector
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instructions under such condition will trap and casuse the termination of the thread.
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arg: The control argument is a 5-bit value consisting of 3 parts, and
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accessed by 3 masks respectively.
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The 3 masks, PR_RISCV_V_VSTATE_CTRL_CUR_MASK,
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PR_RISCV_V_VSTATE_CTRL_NEXT_MASK, and PR_RISCV_V_VSTATE_CTRL_INHERIT
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represents bit[1:0], bit[3:2], and bit[4]. bit[1:0] accounts for the
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enablement status of current thread, and the setting at bit[3:2] takes place
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at next execve(). bit[4] defines the inheritance mode of the setting in
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bit[3:2].
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* :c:macro:`PR_RISCV_V_VSTATE_CTRL_CUR_MASK`: bit[1:0]: Account for the
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Vector enablement status for the calling thread. The calling thread is
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not able to turn off Vector once it has been enabled. The prctl() call
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fails with EPERM if the value in this mask is PR_RISCV_V_VSTATE_CTRL_OFF
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but the current enablement status is not off. Setting
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PR_RISCV_V_VSTATE_CTRL_DEFAULT here takes no effect but to set back
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the original enablement status.
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* :c:macro:`PR_RISCV_V_VSTATE_CTRL_NEXT_MASK`: bit[3:2]: Account for the
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Vector enablement setting for the calling thread at the next execve()
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system call. If PR_RISCV_V_VSTATE_CTRL_DEFAULT is used in this mask,
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then the enablement status will be decided by the system-wide
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enablement status when execve() happen.
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* :c:macro:`PR_RISCV_V_VSTATE_CTRL_INHERIT`: bit[4]: the inheritance
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mode for the setting at PR_RISCV_V_VSTATE_CTRL_NEXT_MASK. If the bit
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is set then the following execve() will not clear the setting in both
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PR_RISCV_V_VSTATE_CTRL_NEXT_MASK and PR_RISCV_V_VSTATE_CTRL_INHERIT.
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This setting persists across changes in the system-wide default value.
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Return value:
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* 0 on success;
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* EINVAL: Vector not supported, invalid enablement status for current or
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next mask;
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* EPERM: Turning off Vector in PR_RISCV_V_VSTATE_CTRL_CUR_MASK if Vector
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was enabled for the calling thread.
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On success:
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* A valid setting for PR_RISCV_V_VSTATE_CTRL_CUR_MASK takes place
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immediately. The enablement status specified in
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PR_RISCV_V_VSTATE_CTRL_NEXT_MASK happens at the next execve() call, or
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all following execve() calls if PR_RISCV_V_VSTATE_CTRL_INHERIT bit is
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set.
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* Every successful call overwrites a previous setting for the calling
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thread.
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* prctl(PR_RISCV_V_GET_CONTROL)
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Gets the same Vector enablement status for the calling thread. Setting for
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next execve() call and the inheritance bit are all OR-ed together.
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Note that ELF programs are able to get the availability of V for itself by
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reading :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the
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auxiliary vector.
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Return value:
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* a nonnegative value on success;
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* EINVAL: Vector not supported.
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2. System runtime configuration (sysctl)
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-----------------------------------------
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To mitigate the ABI impact of expansion of the signal stack, a
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policy mechanism is provided to the administrators, distro maintainers, and
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developers to control the default Vector enablement status for userspace
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processes in form of sysctl knob:
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* /proc/sys/abi/riscv_v_default_allow
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Writing the text representation of 0 or 1 to this file sets the default
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system enablement status for new starting userspace programs. Valid values
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are:
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* 0: Do not allow Vector code to be executed as the default for new processes.
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* 1: Allow Vector code to be executed as the default for new processes.
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Reading this file returns the current system default enablement status.
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At every execve() call, a new enablement status of the new process is set to
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the system default, unless:
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* PR_RISCV_V_VSTATE_CTRL_INHERIT is set for the calling process, and the
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setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
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PR_RISCV_V_VSTATE_CTRL_DEFAULT. Or,
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* The setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
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PR_RISCV_V_VSTATE_CTRL_DEFAULT.
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Modifying the system default enablement status does not affect the enablement
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status of any existing process of thread that do not make an execve() call.
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3. Vector Register State Across System Calls
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---------------------------------------------
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As indicated by version 1.0 of the V extension [1], vector registers are
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clobbered by system calls.
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1: https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc
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