49925c1c5a
StarFive StarLink PMU support monitoring L3 memory system PMU events. Add documentation to describe StarFive StarLink PMU support and it's usage. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com> Link: https://lore.kernel.org/r/20240229072720.3987876-4-jisheng.teoh@starfivetech.com Signed-off-by: Will Deacon <will@kernel.org>
47 lines
1.8 KiB
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47 lines
1.8 KiB
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StarFive StarLink Performance Monitor Unit (PMU)
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StarFive StarLink Performance Monitor Unit (PMU) exists within the
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StarLink Coherent Network on Chip (CNoC) that connects multiple CPU
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clusters with an L3 memory system.
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The uncore PMU supports overflow interrupt, up to 16 programmable 64bit
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event counters, and an independent 64bit cycle counter.
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The PMU can only be accessed via Memory Mapped I/O and are common to the
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cores connected to the same PMU.
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Driver exposes supported PMU events in sysfs "events" directory under::
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/sys/bus/event_source/devices/starfive_starlink_pmu/events/
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Driver exposes cpu used to handle PMU events in sysfs "cpumask" directory
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under::
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/sys/bus/event_source/devices/starfive_starlink_pmu/cpumask/
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Driver describes the format of config (event ID) in sysfs "format" directory
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under::
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/sys/bus/event_source/devices/starfive_starlink_pmu/format/
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Example of perf usage::
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$ perf list
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starfive_starlink_pmu/cycles/ [Kernel PMU event]
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starfive_starlink_pmu/read_hit/ [Kernel PMU event]
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starfive_starlink_pmu/read_miss/ [Kernel PMU event]
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starfive_starlink_pmu/read_request/ [Kernel PMU event]
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starfive_starlink_pmu/release_request/ [Kernel PMU event]
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starfive_starlink_pmu/write_hit/ [Kernel PMU event]
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starfive_starlink_pmu/write_miss/ [Kernel PMU event]
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starfive_starlink_pmu/write_request/ [Kernel PMU event]
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starfive_starlink_pmu/writeback/ [Kernel PMU event]
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$ perf stat -a -e /starfive_starlink_pmu/cycles/ sleep 1
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Sampling is not supported. As a result, "perf record" is not supported.
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Attaching to a task is not supported, only system-wide counting is supported.
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