2 Commits

Author	SHA1	Message	Date
Kumar Gala	aba11fc50c	powerpc/e500mc: flush L2 on NAP for e500mc ... If we have an L2CSR register (e500mc) we need to flush the L2 before going to nap. We use the HW flush mechanism provided in that register. The code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by any code in the kernel. Additionally we didn't reuse the exist L2CR feature bit as this is intended for the 7xxx L2CR register and L2CSR is part of the new Freescale "Book-E" registers. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	2008-06-26 01:49:03 -05:00
Kumar Gala	fc4033b2f8	powerpc/85xx: add DOZE/NAP support for e500 core ... The e500 core enter DOZE/NAP power-saving modes when the core go to cpu_idle routine. The power management default running mode is DOZE, If the user echo 1 > /proc/sys/kernel/powersave-nap the system will change to NAP running mode. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	2008-06-26 01:48:56 -05:00