PCI is faked on these devices by SMM traps. Don't depend on that --
check for the chipset directly instead.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Removing readv from struct mtd_info broke block2mtd. Remove the
reference and the useless default implementation.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Split the core of the read function out and implement
seperate handling functions for software and hardware
ECC.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
The nand driver has a superflous read ready / command
delay in the read functions. This was added to handle
chips which have an automatic read forward. Newer
chips do not have this functionality anymore. Add this
option to avoid the delay / I/O operation. Mark all
large page chips with the new option flag.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
The lock simplifying patch did not move the lock and waitqueue
initialization into the controller allocation patch.
This reinitializes waitqueue and spinlocks also for driver
supplied controller stuctures. Move it into the allocation path.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
The previous change of the command / hardware control allows to
remove the write_byte/word functions completely, as their only
user were nand_command and nand_command_lp.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
The hwcontrol function enforced a step by step state machine
for any kind of hardware chip access. Let the hardware driver
know which control bits are set and inform it about a change
of the control lines. Let the hardware driver write out the
command and address bytes directly. This gives a peformance
advantage for address bus controlled chips and simplifies the
quirks in the hardware drivers.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
MTD clients are agnostic of FLASH which needs ECC suppport.
Remove the functions and fixup the callers.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
First step of modularizing ECC support.
- Move ECC related functionality into a seperate embedded data structure
- Get rid of the hardware dependend constants to simplify new ECC models
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Seperate functionality out of nand_scan so the code is more
readable. No functional change. First step of simplifying
the nand driver.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
The NAND driver used a mix of unsigned char, u_char amd uint8_t
data types. Consolidate to uint8_t usage
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Replace the chip lock by a the controller lock. For simple drivers a
dummy controller structure is created by the scan code.
This simplifies the locking algorithm in nand_get/release_chip().
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Unrolling the loops produces denser and much faster code.
Add a config switch which allows to select the byte order of the
resulting ecc code. The current Linux implementation has a byte
swap versus the SmartMedia specification
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
o Add a flag MTD_BIT_WRITEABLE for devices that allow single bits to be
cleared.
o Replace MTD_PROGRAM_REGIONS with a cleared MTD_BIT_WRITEABLE flag for
STMicro and Intel Sibley flashes with internal ECC. Those flashes
disallow clearing of single bits, unlike regular NOR flashes, so the
new flag models their behaviour better.
o Remove MTD_ECC. After the STMicro/Sibley merge, this flag is only set
and never checked.
Signed-off-by: Joern Engel <joern@wh.fh-wedel.de>
In 2002, STMicro started producing NOR flashes with internal ECC protection
for small blocks (8 or 16 bytes). Support for those flashes was added by me.
In 2005, Intel Sibley flashes copied this strategy and Nico added support for
those. Merge the code for both.
Signed-off-by: Joern Engel <joern@wh.fh-wedel.de>
At least two flashes exists that have the concept of a minimum write unit,
similar to NAND pages, but no other NAND characteristics. Therefore, rename
the minimum write unit to "writesize" for all flashes, including NAND.
Signed-off-by: Joern Engel <joern@wh.fh-wedel.de>
The previous code wouldn't work correctly on architectures which have a
non-empty MODULE_SYMBOL_PREFIX, and this version is neater if slightly
less optimal in the built-in case.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
The patch below adds support for the NAND device on the Amstrad Delta.
This is a 32MiB 8bit Toshiba device, with the data bus connected to the
OMAP MPUIO pins and ALE, CLE, NCE, NRE, NWE and NWP all connected to the
Delta's latch2 16bit latch.
Signed-Off-By: Jonathan McDowell <noodles@earth.li>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
drivers/mtd/devices/docprobe.c: In function `DoC_Probe':
drivers/mtd/devices/docprobe.c:338: warning: assignment from incompatible pointer type
drivers/mtd/devices/docprobe.c:341: warning: assignment from incompatible pointer type
Cc: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
There is a second revision of "mtdconcat NAND/Sibley" patch. I hope
the patch will not get damaged as I'm posting it from gmail account,
thanks to Jorn.
The patch adds previously missing concat_writev(),
concat_writev_ecc(), concat_block_isbad(), concat_block_markbad()
functions to make concatenation layer compatible with Sibley and NAND
chips.
Patch has been cleared from whitespaces, fixed some lines of code as
requested. Also I have added code for alignment check that should
support Jorn's "writesize" patch.
Signed-off-by: Alexander Belyakov <alexander.belyakov@intel.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
The following difference was found between the mainline and linux-mips
kernel. LASAT depends on MTD_CFI.
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
In an unrelated MTD commit, a description about the ms02-nv module
got removed from Kconfig. While I personally agree with this
removal, the module maintainer (Maciej W. Rozycki) would like to
see it added back. In the absense of any consistency regarding
Kconfig descriptions his wish should be followed.
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Acked-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
'oobavail' parameter of mtd_info structure is now propagated to the MTD
partitions
Signed-off-by: Vitaly Wool <vwool@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
This allows for much better abstraction and separation of the XIP and
non-XIP cases with their own specific implementations. This fixes the
case where a timeout was tripped on in the XIP case by the code that
was meant for the non-XIP case only.
This also makes for a nice code reduction.
Signed-off-by: Nicolas Pitre <nico@cam.org>
CC: "Alexey, Korolev" <alexey.korolev@intel.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
The patch below fixes a potential starvation issue that can arise when
there is contention on a chip during a period when a process is
currently writing to it. The starvation is avoided by conditionally
rescheduling when the chip is left in a state usable by other processes.
Signed-off-by: Josh Boyer <jdub@us.ibm.com>
Signed-off-by: Tom Gall <tom_gall@vnet.ibm.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Fix build warnings from drivers/mtd/redboot.c due to
use of `unsigned long` in `struct fis_image_desc` for
fields being passed to swab32s() which expects __u32 *
Change the entries to uint32_t to make them compatible
with the swab32s() function
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
During the last cleanup of the AMD Au1550 NAND driver the old buglet was
reintroduced: as the MEM_STNDCTL register is write-only and seem to always
read as 0x31, read-modify-write to it done in au1xxx_nand_init() will have the
side effect of enabling -RCS0/1 pin override (via bits 4/5 of this reg.), thus
possibly causing a contention on the static bus when the NOR flash (using
-RCS0) or board control status registers (using -RCS2) are read. Luckily, this
goes away with a first NAND access, since au1550_hwcontrol() doesn't try to
read this register before writing anymore.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
We all inherited the same error from the original NAND board driver which
got copied and changed. Fix them all at once...
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
