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Commit Graph

6 Commits

Author SHA1 Message Date
Paul Mackerras
cd74c86bdf perf_counter, powerpc, sparc: Fix compilation after perf_counter_overflow() change
Commit 5622f295 ("x86, perf_counter, bts: Optimize BTS overflow
handling") removed the regs field from struct perf_sample_data and
added a regs parameter to perf_counter_overflow().  This breaks the
build on powerpc (and Sparc) as reported by Sachin Sant:

  arch/powerpc/kernel/perf_counter.c: In function 'record_and_restart':
  arch/powerpc/kernel/perf_counter.c:1165: error: unknown field 'regs' specified in initializer

This adjusts arch/powerpc/kernel/perf_counter.c to correspond with the
new struct perf_sample_data and perf_counter_overflow().

[ v2: also fix Sparc, Markus Metzger <markus.t.metzger@intel.com> ]

Reported-by: Sachin Sant <sachinp@in.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Cc: Markus Metzger <markus.t.metzger@intel.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: benh@kernel.crashing.org
Cc: linuxppc-dev@ozlabs.org
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <19127.8400.376239.586120@drongo.ozlabs.ibm.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-21 09:28:40 +02:00
David S. Miller
b73d884756 sparc64: Initial niagara2 perf counter support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-09-10 07:42:02 -07:00
David S. Miller
660d13765f sparc64: Perf counter 'nop' event is not constant.
On Niagara-2, for example, it's going to be different.  So make
it something specified in sparc_pmu.

Signed-off-by: David S. Miller <davem@davemloft.net>
2009-09-10 07:13:26 -07:00
David S. Miller
496c07e3b4 sparc64: Provide a way to specify a perf counter overflow IRQ enable bit.
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-09-10 07:10:59 -07:00
David S. Miller
91b9286d81 sparc64: Provide hypervisor tracing bit support for perf counters.
A PMU need only specify which bit in the PCR enabled hypervisor
tracing in order to enable this.

This will be used in Niagara-2 perf counter support.

Signed-off-by: David S. Miller <davem@davemloft.net>
2009-09-10 07:09:06 -07:00
David S. Miller
59abbd1e7c sparc64: Initial hw perf counter support.
Only supports one simple counter and only UltraSPARC-IIIi chips.

Signed-off-by: David S. Miller <davem@davemloft.net>
2009-09-10 06:28:20 -07:00