The Torrent SERDES can support at most two different protocols (PHY types).
This only mandates that the device-tree sub-nodes used to represent the
configuration should describe links with at-most two different protocols.
The existing implementation however imposes an artificial constraint that
allows only two links (device-tree sub-nodes). As long as at-most two
protocols are chosen, using more than two links to describe them in an
alternating configuration is still a valid configuration of the Torrent
SERDES.
A 3-Link 2-Protocol configuration of the 4-Lane SERDES can be:
Lane 0 => Protocol 1 => Link 1
Lane 1 => Protocol 1 => Link 1
Lane 2 => Protocol 2 => Link 2
Lane 3 => Protocol 1 => Link 3
A 4-Link 2-Protocol configuration of the 4-Lane SERDES can be:
Lane 0 => Protocol 1 => Link 1
Lane 1 => Protocol 2 => Link 2
Lane 2 => Protocol 1 => Link 3
Lane 3 => Protocol 2 => Link 4
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240805092607.143869-1-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
'cdns_torrent_refclk_driver_mux_table' is not modified in this driver.
And it is only used as a "const u32 *".
Constifying this structure moves some data to a read-only section, so
increase overall security.
On a x86_64, with allmodconfig:
Before:
======
text data bss dec hex filename
93578 4798 16 98392 18058 drivers/phy/cadence/phy-cadence-torrent.o
After:
=====
text data bss dec hex filename
93606 4790 16 98412 1806c drivers/phy/cadence/phy-cadence-torrent.o
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/34e23ceb6b7b7eb730ee8deee21d231b504dc65f.1720718240.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
'struct cdns_torrent_vals' is not modified in this driver.
Constifying this structure moves some data to a read-only section, so
increase overall security.
On a x86_64, with allmodconfig:
Before:
======
text data bss dec hex filename
92234 6078 16 98328 18018 drivers/phy/cadence/phy-cadence-torrent.o
After:
=====
text data bss dec hex filename
93578 4798 16 98392 18058 drivers/phy/cadence/phy-cadence-torrent.o
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/d9d135ee9b806726766a1bc5e1404267939aa637.1720718240.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
'struct cdns_torrent_vals_entry' is not modified in this driver.
Constifying this structure moves some data to a read-only section, so
increase overall security.
On a x86_64, with allmodconfig:
Before:
======
text data bss dec hex filename
85130 13214 16 98360 18038 drivers/phy/cadence/phy-cadence-torrent.o
After:
=====
text data bss dec hex filename
92234 6078 16 98328 18018 drivers/phy/cadence/phy-cadence-torrent.o
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/dcc4e539999a840b3fd8f40fd8fd7523390232ac.1720718240.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
'struct cdns_reg_pairs' is not modified in this driver.
Constifying this structure moves some data to a read-only section, so
increase overall security.
On a x86_64, with allmodconfig:
Before:
======
text data bss dec hex filename
78154 20222 16 98392 18058 drivers/phy/cadence/phy-cadence-torrent.o
After:
=====
text data bss dec hex filename
85130 13214 16 98360 18038 drivers/phy/cadence/phy-cadence-torrent.o
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/803684a6f0c24d7e091dc8d285dd49c6fd31a010.1720718240.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
cdns_torrent_dp_set_power_state() does not consider that ret might be
overwritten. Add return value check of regmap_read_poll_timeout() after
register read in cdns_torrent_dp_set_power_state().
Fixes: 5b16a790f1 ("phy: cadence-torrent: Reorder few functions to remove function declarations")
Signed-off-by: Ma Ke <make24@iscas.ac.cn>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240702032042.3993031-1-make24@iscas.ac.cn
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add suspend and resume support.
The already_configured flag is cleared during the suspend stage to force
the PHY initialization during the resume stage.
Co-developed-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-8-f15815833974@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Even if a PHY is already configured, the PHY operations are needed during
resume stage, as the PHY is in reset state.
The noop_ops PHY operations is removed to always have PHY operations.
The already_configured flag is checked at the begening of init, configure
and poweron operations to keep the already_configured behaviour.
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-7-f15815833974@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Resets are needed during suspend and resume stages.
So they shall be registered during the probe even the phy is already
initialized.
The function cdns_torrent_reset is renamed cdns_torrent_of_get_reset() to
make it clear.
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-5-f15815833974@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Extract calls to clk_get from cdns_torrent_clk into a separate function.
It needs to call cdns_torrent_clk at resume without looking up the clock.
Co-developed-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-4-f15815833974@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add a separate compatible and registers map table for TI J7200.
TI J7200 uses Torrent SD0805 version which is a special version
derived from Torrent SD0801 with some differences in register
configurations.
Add register sequences for USXGMII(156.25MHz) + SGMII/QSGMII(100MHz)
multilink config for TI J7200. USXGMII uses PLL0 and SGMII/QSGMII
uses PLL1.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240104133013.2911035-6-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Torrent PHY can have separate input reference clocks for PLL0 and PLL1.
Add support for dual reference clock multilink configurations.
Add register sequences for PCIe(100MHz) + USXGMII(156.25MHz) multilink
configuration. PCIe uses PLL0 and USXGMII uses PLL1.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240104133013.2911035-3-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> # for drivers/phy/phy-can-transceiver.c
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20230714174841.4061919-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Instead of a 3D matrix use a key:value pair table for link_cmn_vals,
xcvr_diag_vals, pcs_cmn_vals, phy_pma_cmn_vals, cmn_vals,
tx_ln_vals and rx_ln_vals. This makes it scaleable for multiple
reference clocks.
Wherever both CDNS and TI use the same settings, reuse the same data.
Introduce CLK_ANY and ANY_SSC enums which are used if the setting
is independent of clock rate or SSC type.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20230530143853.26571-3-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
- New Support
- Debugfs support for phy core and mediatek driver
- Hisilicon inno-usb2-phy driver supporting Hi3798MV100
- Qualcomm SGMII SerDes PHY driver, SM6115 & QCM2290 QMP-USB support,
SA8775P USB PHY & USB3 UNI support, QUSB2 support for IPQ9574, IPQ9574 USB3 PHY
- Updates
- Sparx5 serdes phy power optimzation
- cadence salvo usb properties and updates and torrent DP with PCIe &
USB support
- Yaml conversion for Broadcom kona USB bindings and MXS USB binding
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE+vs47OPLdNbVcHzyfBQHDyUjg0cFAmSlyssACgkQfBQHDyUj
g0d6yg/9Ghx1aHTN3DgdXQ0DNSv79IlQXSMP3KXQJgRxmMbdJyVIv/FdnEYRnXFD
Rhvfal/fbBiGh7VskrcuYjW8ijQ4cSyvcgu+2FeuPoRq/0x7S3XMlw/2Fex6H1wU
wCS2V3RVuePEQRYeO3eVHQyVxWEa8Qk+2Ry0KG1s9DBIZgeMuU2f1FRED6p9Ayz8
Q1dBA/mVpPnEFhhIaO66IpvTLZ2M8x+mk0wFLtDl7f5ImFz0A7lM+Dfr42rJ0rWi
A1YbTSpEMTKVaoNKhAxrqdIEZzlQ/sPWiqeDwA+Ao9l1N8Dn0UWVJfXIuwBi/XzK
9552nsWwQE4ikiEU4+mxq7pZqrlT5kt8axxdvIC9MH70yRTdrEH34IbOb2IaD+GM
oKW++7ZVyeFmSmy5XezrgYbHzEdh2HBESUrbrLUg0qFOR+5lccDOI2KxOKx08Myw
pLpjROADwwUpa2PJ3hTRhCGURPXRVPQuB2Du7s1ILH6Fckeq9rIbmYEVcKUt8dgu
ZJXCRMG7nEKmT5G6XND7pHfFmt+oA4zdQxnUpBOgY64RIcllbpkv1smbJYlyqfKG
1pvOSkzriacldQSVSuzUiQ3CFgVN1+NjBBSLHDd5UWilEKVCjP5+gNpLhg2oAiXu
VK6j8MeHOmVgVH2V2kSnNU9oUBorddoMiTua7ci14NbwqVwwjUU=
=ReXo
-----END PGP SIGNATURE-----
Merge tag 'phy-for-6.5_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul:
"New Support:
- Debugfs support for phy core and mediatek driver
- Hisilicon inno-usb2-phy driver supporting Hi3798MV100
- Qualcomm SGMII SerDes PHY driver, SM6115 & QCM2290 QMP-USB support,
SA8775P USB PHY & USB3 UNI support, QUSB2 support for IPQ9574,
IPQ9574 USB3 PHY
UpdatesL
- Sparx5 serdes phy power optimzation
- cadence salvo usb properties and updates and torrent DP with PCIe &
USB support
- Yaml conversion for Broadcom kona USB bindings and MXS USB binding"
* tag 'phy-for-6.5_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (67 commits)
dt-bindings: phy: brcm,brcmstb-usb-phy: Fix error in "compatible" conditional schema
dt-bindings: phy: mixel,mipi-dsi-phy: Remove assigned-clock* properties
dt-bindings: phy: intel,combo-phy: restrict node name suffixes
dt-bindings: phy: qcom,usb-hs-phy: Add compatible
phy: tegra: xusb: check return value of devm_kzalloc()
phy: qcom: qmp-combo: fix Display Port PHY configuration for SM8550
phy: qcom: add the SGMII SerDes PHY driver
dt-bindings: phy: describe the Qualcomm SGMII PHY
phy: qualcomm: fix indentation in Makefile
phy: usb: suppress OC condition for 7439b2
phy: usb: Turn off phy when port is in suspend
phy: tegra: xusb: Clear the driver reference in usb-phy dev
dt-bindings: phy: mxs-usb-phy: add imx8ulp and imx8qm compatible
dt-bindings: phy: mxs-usb-phy: convert to DT schema format
dt-bindings: phy: qcom,qmp-usb: fix bindings error
dt-bindings: phy: qcom,qmp-ufs: fix the sc8180x regs
dt-bindings: phy: qcom,qmp-pcie: fix the sc8180x regs
phy: mediatek: tphy: add debugfs files
phy: core: add debugfs files
phy: fsl-imx8mp-usb: add support for phy tuning
...
The Cadence Torrent refclk clock implements a mux with a set_parent
hook, but doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The latter case would be equivalent to setting the flag
CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook
to __clk_mux_determine_rate(). Indeed, if no determine_rate
implementation is provided, clk_round_rate() (through
clk_core_round_rate_nolock()) will call itself on the parent if
CLK_SET_RATE_PARENT is set, and will not change the clock rate
otherwise.
And if it was an oversight, then we are at least explicit about our
behavior now and it can be further refined down the line.
Since the CLK_SET_RATE_NO_REPARENT flag was already set though, it seems
unlikely.
Cc: Kishon Vijay Abraham I <kishon@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: linux-phy@lists.infradead.org
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-42-971d5077e7d2@cerno.tech
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add multilink DP configuration support for 100MHz reference clock rate.
This is the only clock rate supported currently for multilink PHY
configurations. Also, add PCIe + DP multiprotocol multilink register
configuration sequences for 100MHz refclk with no SSC.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20230418173157.25607-4-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This patch prepares driver for multilink DP support as well as for
multiprotocol PHY configurations involving DP as one of the required
protocols. This needs changes in functions configuring default single
link DP with master lane 0 to support non-zero master lane values and
associated PLL configurations.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20230418173157.25607-3-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Torrent PHY PLL0 or PLL1 is used for DP depending on the single link or
multilink protocol configuration for which PHY is configured. In multilink
configurations with other protocols, either PLL0 or PLL1 will be used
for DP. For single link DP, both PLLs need to be configured at POR.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20230418173157.25607-2-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230307115900.2293120-6-u.kleine-koenig@pengutronix.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
The driver state struct for the sierra PHY driver has a field named
`regmap` that is never referenced. Remove it since it is unused.
Not that there are separate fields of type `struct regmap` for the
individual sections of the device's register map. These other regmaps are
used and not affected by the patch.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20220707071722.44201-2-lars@metafoo.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Use the macro 'swap()' defined in 'include/linux/minmax.h' to avoid
opencoding it.
Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Yang Guang <yang.guang5@zte.com.cn>
Link: https://lore.kernel.org/r/20211104065233.1833499-1-yang.guang5@zte.com.cn
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add support to output received reference clock. Model the received
reference clock as an alternate parent of reference clock driver
clock. When received refclk is selected to output on cmn_refclk_p/m,
this is the internal reference clock driven on the pma_cmn_refclk_int.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210922123735.21927-5-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
When reference clock driver is enabled, either derived or received refclk
is output on cmn_refclk_p/m. Update the reference clock driver
implementation by modelling reference clock driver as a "clock" with
derived reference clock set as its default parent. The support for
received reference clock will be added in a separate patch.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210922123735.21927-4-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
PIPE PHY status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-10-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add debug information in probe regarding PHY configuration parameters
like single link or multilink protocol along with number of lanes
used for each protocol link.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-9-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Torrent PHY driver currently supports single link DP configuration.
Prepare driver to support multilink DP configurations by adding
separate functions for common initialization sequence.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210728145454.15945-8-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add PHY registers for single link DP in array format to simplify
code and to improve readability. This supports already supported
frequencies for DP of 19.2MHz and 25MHz.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-6-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Torrent PHY supports multiple serdes standards with different input
reference clock frequencies. PHY register values differ based on the
reference clock rate. Add PHY input reference clock frequency as a
new dimension to select proper register configuration. No functional
change is intended.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-5-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Torrent PHY supports different input reference clock frequencies.
Register configurations will be different based on reference clock value.
Prepare driver to support such multiple reference clock frequencies.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210728145454.15945-4-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
The Torrent spec specifies delay of 660.5us after phy_reset is
asserted by the controller. To be on the safe side provide a delay
of 5ms to 10ms in ->phy_on() callback where the SERDES is already
configured in bootloader.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210330110138.24356-6-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
No functional change. Since the reset controls obtained in
Torrent is exclusively used by the Torrent device, use
exclusive reset control request API calls.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210330110138.24356-5-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Do not configure torrent SERDES if it's already configured.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210330110138.24356-4-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
No functional change intended. Group reset APIs and clock APIs in
preparation for adding support to skip configuration if the SERDES
is already configured by bootloader.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210330110138.24356-3-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
No functional change. In order to have a single header file for all
Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is
in preparation for adding Cadence Sierra SERDES specific macros.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210319124128.13308-9-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Update PCIe + USB register sequences for correct PLL1 clock configuration.
Also, update sequences for other USB configurations with dependent changes.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/1614838096-32291-5-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
For PCIe + QSGMII configuration where QSGMII was using PLL1 and was
expecting 10GHz clock, configuration was giving 8GHz clock. Update
register sequences to get correct PLL1 configuration.
Also, update single link PCIe and single link SGMII/QSGMII configurations
with related changes.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/1614838096-32291-2-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external
reference clock. cmn_refclk_<p/m> can also be configured to output the
reference clock. Model this derived reference clock as a "clock" so that
platforms like AM642 EVM can enable it.
This is used by PCIe to use the same refclk both in local SERDES
and remote device. Add support here to drive refclk out.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210310120840.16447-7-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This error path should return -EINVAL, but currently it returns
success.
Fixes: d09945eaca ("phy: cadence-torrent: Check total lane count for all subnodes is within limit")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lore.kernel.org/r/X9s7Wxq+b6ls0q7o@mwanda
Signed-off-by: Vinod Koul <vkoul@kernel.org>
