The WM8994 can output a clock derived from its internal SYSCLK, called
OPCLK. The rate can be selected as a sysclk, with a division from the
SYSCLK rate specified (multiplied by 10 since a division of 5.5 is
supported) and the clock can be disabled by specifying a divisor of
zero.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
The WM8994 FLL can be clocked from one of four inputs, the two MCLKs and
the LRCLK and BCLK of the AIF associated with the FLL. Allow all four
inputs to be used rather than defaulting to MCLK1.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Support interrupt based microphone bias detection. The WM8994 has two
microphone bias supplies, with detection supported on both. Detection
using GPIOs together with the standard GPIO based jack framework is
already supported via the platform data for the WM8994 core driver.
Note that as well as the microphone bias itself the system clock and
whichever AIF clock is supplying the system clock will need to be
enabled for detection to function.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The WM8994 is a highly integrated ultra-low power hi-fi audio subsystem
designed for smartphones and other portable devices rich in multimedia
features. It provides advanced digital mixing facilities enabling low
power high quality interconnection of CPU, baseband and other audio
sources through flexible digital and analogue routing, and integrates
a class W headphone driver and stereo class D speaker drivers.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
