Make definitions for struct e820entry and struct e820map
consistent between i386 and x86-64.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
The relocatable kernel code needs a scratch field for the decompressor
to determine its own location. It was using a location inside
struct screen_info; reserve a free location and document it as scratch
instead.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Some Intel features are spread around in different CPUID leafs like 0x5,
0x6 and 0xA. Make this feature detection code common across i386 and
x86_64.
Display Intel Dynamic Acceleration feature in /proc/cpuinfo. This feature
will be enabled automatically by current acpi-cpufreq driver.
Refer to Intel Software Developer's Manual for more details about the feature.
Thanks to hpa (H Peter Anvin) for the making the actual code detecting the
scattered features data-driven.
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
struct screen_info has unaligned members, it needs to be packed.
In the process, fix the naming of some of the members, which don't
belong in this structure but are part of it anyway.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
The X86_MINIMUM_CPU_MODEL name isn't really right, so change it to
X86_MINIMUM_CPU_FAMILY. Also, the default minimum should be 3, not 0.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Unify the handling of the CPU features vectors between i386 and x86-64.
This also adopts the collapsing of features which are required at
compile-time into constant tests from x86-64 to i386.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
include/asm-i386/boot.h incorrectly has the multiple include guards
as _LINUX_BOOT_H instead of _ASM_BOOT_H. Fix.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
An ST-506 disk these days is pretty much someone trying to pull ancient
data using an auxilliary controller. Pulling data from the BIOS or CMOS
is just plain wrong, since it's likely to be the primary OS disk... and
would be user-entered data anyway. Instead, require the user enters it
on the command line.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Change MAINTAINERS to formally take responsibility for the i386 boot code.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
While the PC speaker is wired up to the i8254 there is more to the i8254
than just the PC speaker so this code was getting in the way under its
current name.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The only pseudo-legitimate MIPS user of genrtc was a systems that doesn't
have an RTC in hardware at all. At this point faking one is a little
pointless ...
Fixes this warning:
arch/mips/pci/pci.c:284:18: warning: symbol 'dev' shadows an earlier one
arch/mips/pci/pci.c:272:17: originally declared here
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
To support multiple TC microthreads acting as "CPUs" within a VPE,
VPE-wide interrupt mask bits must be specially manipulated during
interrupt handling. To support legacy drivers and interrupt controller
management code, SMTC has a "backstop" to track and if necessary restore
the interrupt mask. This has some performance impact on interrupt service
overhead. Disable it only if you know what you are doing.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This fixes this sparse warning:
arch/mips/lib/uncached.c:38:22: warning: symbol 'run_uncached' was not declared. Should it be static?
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Also include tlbdebug.h in dump_tlb.c and r3k_dump_tlb.c.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch is an workaround for these sparse warnings:
include2/asm/mmu_context.h:172:2: warning: symbol 'flags' shadows an earlier one
include2/asm/mmu_context.h:133:16: originally declared here
include2/asm/mmu_context.h:232:2: warning: symbol 'flags' shadows an earlier one
include2/asm/mmu_context.h:203:16: originally declared here
include2/asm/mmu_context.h:277:3: warning: symbol 'flags' shadows an earlier one
include2/asm/mmu_context.h:250:16: originally declared here
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
CKSEG1ADDR() returns unsigned int value on 32bit kernel. Cast it to
unsigned long to get rid of this warning:
include2/asm/io.h:215:12: warning: cast adds address space to expression (<asn:2>)
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Use physical address for 82596 and 53c710 base address
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
When running Linux in non-secure mode (on ARM1176 for example),
depending on the CP15 secure configuration register, the CPSR.F bit
(6) might only be modified from the secure mode. However, the
valid_user_regs() function checks for this bit being cleared. With
commit a6c61e9d, a SIGSEGV is forced in handle_signal() if the user
registers are not considered valid.
The patch also ensures that the CPSR.A bit is cleared and the USR mode
is set if the CPU does not support the 26bit user mode.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The patch moves the HWCAP definitions and the extern elf_hwcap
declaration to the hwcap.h header file.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This allows individual CPU support to determine which platform
devices should be registered. Also fix a copy-n-paste bug in
the I2C power platform device entry.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The RTC library code contains everything necessary to set the
system time from the RTC; for similar reasons as the previous
commit, it's far better to let the RTC library code sort this
out rather than implement something which might not be
appropriate for everyone.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the RTC management over a suspend/resume cycle. Firstly,
we may not be using the internal RTC for time keeping; some
platforms have an external RTC for this inspite of the PXA having
an internal RTC. Secondly, the RTC library code handles updating
system time on resume.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Since the number of dma channels varies between pxa25x and pxa27x, it
introduces some specific code in dma.c. This patch moves the specific
code to pxa25x.c and pxa27x.c and makes dma.c more generic.
1. add pxa_init_dma() for dma initialization, the number of channels
are passed in by the argument
2. add a "prio" field to the "struct pxa_dma_channel" for the channel
priority, and is initialized in pxa_init_dma()
3. use a general priority comparison with the channels "prio" field so
to remove the processor specific pxa_for_each_dma_prio macro, this
is not lightning fast as the original one, but it is acceptable as
it happens when requesting dma, which is usually not so performance
critical
Signed-off-by: eric miao <eric.miao@marvell.com>
Acked-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
/* should be ok this time, I aligned this patch to your arm:pxa2.mbox */
1. move pxa25x specific IRQ initialization code to pxa25x_init_irq()
and pxa27x code to pxa27x_init_irq(), remove pxa_init_irq()
2. replace all pxa_init_irq() with their PXA25x or PXA27x specific
functions
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ICIP2 is not examined during IRQ entrance, this patch add the
checking if the processor is PXA27x or later, with CoreG bits
in CPUID (Core Generation) > 1
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1. use GPIO_IRQ_mask[] to select those bits of interest, actually
only those "unmasked" GPIO IRQs with their corresponding bits
in GPIO_IRQ_mask[] set to "1" should be checked
2. remove #ifdef PXA_LAST_GPIO > 96 .. #endif, GPIO_IRQ_mask[]
is used to mask out the irrelevant bits, so that even though
the GEDR3 on PXA25x is reserved, it will be masked, and the
following code will never run. Another point is that GPIO85-
GPIO95 bits within GEDR2 will also be masked out on PXA25x
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
move the GPIO IRQ initialization code to pxa_init_irq_gpio()
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1. move low IRQ initialization code to pxa_init_irq_low()
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1. define PXA_GPIO_IRQ_BASE to be right after the internal IRQs,
and define PXA_GPIO_IRQ_NUM to be 128 for all PXA2xx variants
2. make the code specific to the high IRQ numbers (32..64) to be
PXA27x specific
3. add a function pxa_init_irq_high() to initialize the internal
high IRQ chip, the invoke of this function could be moved to
PXA27x specific initialization code
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1. PXA_IRQ_SKIP is defined to be 7 on PXA25x so that the first IRQ
starts from zero. This makes IRQ numbering inconsistent between
PXA25x and PXA27x. Remove this macro so that the same IRQ_XXXXX
definition has the same value on both PXA25x and PXA27x.
2. make IRQ_SSP3..IRQ_PWRI2C valid only if PXA27x is defined, this
avoids unintentional use of these macros on PXA25x
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
pxa_pm_prepare() tried to validate the suspend method type. As
noted in previous commits:
eb9289eb209c372d06cee8c9c50269
the checking of the suspend type in the 'prepare' method is the
wrong place to do this; use the 'valid' method instead. This
means that pxa_pm_prepare() can be entirely removed.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Move the pm_ops structure into the PXA25x and PXA27x support
files. Remove the old pxa_pm_prepare() function, and rename
the both pxa_cpu_pm_prepare() functions as pxa_pm_prepare().
We'll fix that later.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
pxamci.h redefines the MMC registers differently so they can be used
with ioremap. Remove the incompatible definitions from pxa-regs.h.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
pxa_pm_finish() does nothing but return zero. The core code
does nothing with this return value, and will not try to call
the finish method in the pm_ops structure if it is NULL.
Therefore, we can remove this useless function.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This driver has been broken forever. It depends on i2c-algo-8xx which
has never been in the mainline kernel.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Work around a problem reported on:
http://ozlabs.org/pipermail/linuxppc-embedded/2005-July/019038.html
Without this patch I2C on mpc5200 becomes unusable after a while.
Tested on mpc5200 boards by Matthias Fechner and me.
Signed-off-by: Domen Puncer <domen.puncer@telargo.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
