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Commit Graph

9 Commits

Author SHA1 Message Date
Eric Miao
c4a90588fa ARM: dove: fix __io() definition to use bus based offset
Signed-off-by: Eric Miao <eric.miao@canonical.com>
Acked-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
2010-09-19 22:43:42 -04:00
Saeed Bishara
16bc90af15 [ARM] Dove: platform device registration for the sdio interfaces
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
2010-07-16 22:01:59 -04:00
Russell King
988addf82e Merge branch 'origin' into devel-stable
Conflicts:
	arch/arm/mach-mx2/devices.c
	arch/arm/mach-mx2/devices.h
	sound/soc/pxa/pxa-ssp.c
2010-03-08 20:21:04 +00:00
Russell King
2741ecb4ce Merge branch 'misc2' into devel 2010-02-25 22:09:41 +00:00
Fenkart/Bostandzhyan
c931b4f655 ARM: 5928/1: Change type of VMALLOC_END to unsigned long.
Makes it consistent with VMALLOC_START

Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-15 21:40:33 +00:00
Tony Lindgren
4e6d488af3 ARM: 5910/1: ARM: Add tmp register for addruart and loadsp
Otherwise more complicated uart configuration won't be possible.
We can use r1 for tmp register for both head.S and debug.S.

NOTE: This patch depends on another patch to add the the tmp register
into all debug-macro.S files. That can be done with:

$ sed -i -e "s/addruart,rx|addruart, rx/addruart, rx, tmp/"
	arch/arm/*/include/*/debug-macro.S

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-12 17:27:52 +00:00
H Hartley Sweeten
639b9be60e mach-dove/common.c: remove unnecessary (void *) casts
The (void *) cast is not needed when setting dev.platform_data to the
address of the data. Remove the casts.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2010-02-05 00:27:03 -05:00
Lennert Buytenhek
573a652fb0 ARM: Add Tauros2 L2 cache controller support
Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-11-27 15:43:21 -05:00
Saeed Bishara
edabd38e1a ARM: add base support for Marvell Dove SoC
The Marvell Dove (88AP510) is a high-performance, highly integrated,
low power SoC with high-end ARM-compatible processor (known as PJ4),
graphics processing unit, high-definition video decoding acceleration
hardware, and a broad range of peripherals.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-11-27 15:43:06 -05:00