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pmdomain: renesas: rcar-sysc: Add R-Car M3-W power-off delay quirk

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R-Car M3-W needs a delay of 1 µs before powering off the A3IR and A3VC
power domains.  Add support for this using a new flag, which indicates
that a power area is subject to this quirk.

Inspired by a patch in the BSP by Dien Pham.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/ecbc3465c598084c904dd3714e2894463094ed9a.1713348705.git.geert+renesas@glider.be
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Geert Uytterhoeven 2024-04-17 12:29:25 +02:00 committed by Ulf Hansson
parent c8d8770444
commit fdea114ac2
3 changed files with 9 additions and 2 deletions
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6
drivers/pmdomain/renesas/r8a77960-sysc.c
View File

@ -32,12 +32,14 @@ static const struct rcar_sysc_area r8a77960_areas[] __initconst = {
{ "ca53-cpu3", 0x200, 3, R8A7796_PD_CA53_CPU3, R8A7796_PD_CA53_SCU,
PD_CPU_NOCR },
{ "cr7", 0x240, 0, R8A7796_PD_CR7, R8A7796_PD_ALWAYS_ON },
{ "a3vc", 0x380, 0, R8A7796_PD_A3VC, R8A7796_PD_ALWAYS_ON },
{ "a3vc", 0x380, 0, R8A7796_PD_A3VC, R8A7796_PD_ALWAYS_ON,
PD_OFF_DELAY },
{ "a2vc0", 0x3c0, 0, R8A7796_PD_A2VC0, R8A7796_PD_A3VC },
{ "a2vc1", 0x3c0, 1, R8A7796_PD_A2VC1, R8A7796_PD_A3VC },
{ "3dg-a", 0x100, 0, R8A7796_PD_3DG_A, R8A7796_PD_ALWAYS_ON },
{ "3dg-b", 0x100, 1, R8A7796_PD_3DG_B, R8A7796_PD_3DG_A },
{ "a3ir", 0x180, 0, R8A7796_PD_A3IR, R8A7796_PD_ALWAYS_ON },
{ "a3ir", 0x180, 0, R8A7796_PD_A3IR, R8A7796_PD_ALWAYS_ON,
PD_OFF_DELAY },
};

4
drivers/pmdomain/renesas/rcar-sysc.c
View File

@ -90,6 +90,10 @@ static int rcar_sysc_pwr_on_off(const struct rcar_sysc_pd *pd, bool on)
if (ret)
return -EAGAIN;
/* Power-off delay quirk */
if (!on && (pd->flags & PD_OFF_DELAY))
udelay(1);
/* Submit power shutoff or power resume request */
iowrite32(BIT(pd->chan_bit), rcar_sysc_base + pd->chan_offs + reg_offs);

1
drivers/pmdomain/renesas/rcar-sysc.h
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@ -16,6 +16,7 @@
#define PD_CPU BIT(0) /* Area contains main CPU core */
#define PD_SCU BIT(1) /* Area contains SCU and L2 cache */
#define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */
#define PD_OFF_DELAY BIT(3) /* Area is subject to power-off delay quirk */
#define PD_CPU_CR PD_CPU /* CPU area has CR (R-Car H1) */
#define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */