powerpc64/bpf: jit support for signed division and modulo
Add jit support for sign division and modulo. Tested using test_bpf module. Signed-off-by: Artem Savkov <asavkov@redhat.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20240517075650.248801-6-asavkov@redhat.com
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@ -536,6 +536,7 @@
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#define PPC_RAW_MULI(d, a, i) (0x1c000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
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#define PPC_RAW_DIVW(d, a, b) (0x7c0003d6 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
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#define PPC_RAW_DIVWU(d, a, b) (0x7c000396 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
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#define PPC_RAW_DIVD(d, a, b) (0x7c0003d2 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
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#define PPC_RAW_DIVDU(d, a, b) (0x7c000392 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
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#define PPC_RAW_DIVDE(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
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#define PPC_RAW_DIVDE_DOT(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
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@ -510,20 +510,33 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
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case BPF_ALU | BPF_DIV | BPF_X: /* (u32) dst /= (u32) src */
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case BPF_ALU | BPF_MOD | BPF_X: /* (u32) dst %= (u32) src */
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if (BPF_OP(code) == BPF_MOD) {
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EMIT(PPC_RAW_DIVWU(tmp1_reg, dst_reg, src_reg));
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if (off)
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EMIT(PPC_RAW_DIVW(tmp1_reg, dst_reg, src_reg));
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else
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EMIT(PPC_RAW_DIVWU(tmp1_reg, dst_reg, src_reg));
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EMIT(PPC_RAW_MULW(tmp1_reg, src_reg, tmp1_reg));
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EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg));
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} else
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EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, src_reg));
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if (off)
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EMIT(PPC_RAW_DIVW(dst_reg, dst_reg, src_reg));
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else
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EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, src_reg));
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goto bpf_alu32_trunc;
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case BPF_ALU64 | BPF_DIV | BPF_X: /* dst /= src */
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case BPF_ALU64 | BPF_MOD | BPF_X: /* dst %= src */
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if (BPF_OP(code) == BPF_MOD) {
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EMIT(PPC_RAW_DIVDU(tmp1_reg, dst_reg, src_reg));
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if (off)
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EMIT(PPC_RAW_DIVD(tmp1_reg, dst_reg, src_reg));
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else
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EMIT(PPC_RAW_DIVDU(tmp1_reg, dst_reg, src_reg));
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EMIT(PPC_RAW_MULD(tmp1_reg, src_reg, tmp1_reg));
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EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg));
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} else
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EMIT(PPC_RAW_DIVDU(dst_reg, dst_reg, src_reg));
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if (off)
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EMIT(PPC_RAW_DIVD(dst_reg, dst_reg, src_reg));
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else
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EMIT(PPC_RAW_DIVDU(dst_reg, dst_reg, src_reg));
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break;
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case BPF_ALU | BPF_MOD | BPF_K: /* (u32) dst %= (u32) imm */
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case BPF_ALU | BPF_DIV | BPF_K: /* (u32) dst /= (u32) imm */
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@ -544,19 +557,31 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
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switch (BPF_CLASS(code)) {
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case BPF_ALU:
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if (BPF_OP(code) == BPF_MOD) {
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EMIT(PPC_RAW_DIVWU(tmp2_reg, dst_reg, tmp1_reg));
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if (off)
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EMIT(PPC_RAW_DIVW(tmp2_reg, dst_reg, tmp1_reg));
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else
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EMIT(PPC_RAW_DIVWU(tmp2_reg, dst_reg, tmp1_reg));
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EMIT(PPC_RAW_MULW(tmp1_reg, tmp1_reg, tmp2_reg));
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EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg));
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} else
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EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, tmp1_reg));
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if (off)
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EMIT(PPC_RAW_DIVW(dst_reg, dst_reg, tmp1_reg));
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else
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EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, tmp1_reg));
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break;
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case BPF_ALU64:
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if (BPF_OP(code) == BPF_MOD) {
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EMIT(PPC_RAW_DIVDU(tmp2_reg, dst_reg, tmp1_reg));
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if (off)
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EMIT(PPC_RAW_DIVD(tmp2_reg, dst_reg, tmp1_reg));
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else
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EMIT(PPC_RAW_DIVDU(tmp2_reg, dst_reg, tmp1_reg));
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EMIT(PPC_RAW_MULD(tmp1_reg, tmp1_reg, tmp2_reg));
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EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg));
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} else
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EMIT(PPC_RAW_DIVDU(dst_reg, dst_reg, tmp1_reg));
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if (off)
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EMIT(PPC_RAW_DIVD(dst_reg, dst_reg, tmp1_reg));
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else
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EMIT(PPC_RAW_DIVDU(dst_reg, dst_reg, tmp1_reg));
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break;
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}
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goto bpf_alu32_trunc;
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