dt-bindings: clock: add Amlogic C3 peripherals clock controller
Add the peripherals clock controller dt-bindings for Amlogic C3 SoC family Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Co-developed-by: Chuan Liu <chuan.liu@amlogic.com> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/r/20240522082727.3029656-4-xianwei.zhao@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Xianwei Zhao
Jerome Brunet
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/amlogic,c3-peripherals-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic C3 series Peripheral Clock Controller
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Jerome Brunet <jbrunet@baylibre.com>
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- Xianwei Zhao <xianwei.zhao@amlogic.com>
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- Chuan Liu <chuan.liu@amlogic.com>
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properties:
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compatible:
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const: amlogic,c3-peripherals-clkc
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reg:
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maxItems: 1
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clocks:
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minItems: 16
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items:
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- description: input oscillator (usually at 24MHz)
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- description: input oscillators multiplexer
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- description: input fix pll
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- description: input fclk div 2
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- description: input fclk div 2p5
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- description: input fclk div 3
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- description: input fclk div 4
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- description: input fclk div 5
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- description: input fclk div 7
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- description: input gp0 pll
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- description: input gp1 pll
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- description: input hifi pll
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- description: input sys clk
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- description: input axi clk
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- description: input sys pll div 16
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- description: input cpu clk div 16
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- description: input pad clock for rtc clk (optional)
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clock-names:
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minItems: 16
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items:
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- const: xtal_24m
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- const: oscin
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- const: fix
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- const: fdiv2
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- const: fdiv2p5
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- const: fdiv3
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- const: fdiv4
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- const: fdiv5
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- const: fdiv7
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- const: gp0
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- const: gp1
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- const: hifi
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- const: sysclk
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- const: axiclk
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- const: sysplldiv16
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- const: cpudiv16
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- const: pad_osc
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"#clock-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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apb {
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#address-cells = <2>;
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#size-cells = <2>;
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clock-controller@0 {
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compatible = "amlogic,c3-peripherals-clkc";
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reg = <0x0 0x0 0x0 0x49c>;
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#clock-cells = <1>;
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clocks = <&xtal_24m>,
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<&scmi_clk 8>,
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<&scmi_clk 12>,
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<&clkc_pll 3>,
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<&clkc_pll 5>,
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<&clkc_pll 7>,
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<&clkc_pll 9>,
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<&clkc_pll 11>,
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<&clkc_pll 13>,
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<&clkc_pll 15>,
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<&scmi_clk 13>,
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<&clkc_pll 17>,
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<&scmi_clk 9>,
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<&scmi_clk 10>,
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<&scmi_clk 14>,
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<&scmi_clk 15>;
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clock-names = "xtal_24m",
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"oscin",
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"fix",
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"fdiv2",
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"fdiv2p5",
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"fdiv3",
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"fdiv4",
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"fdiv5",
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"fdiv7",
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"gp0",
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"gp1",
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"hifi",
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"sysclk",
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"axiclk",
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"sysplldiv16",
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"cpudiv16";
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};
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};
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212
include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h
Normal file
212
include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h
Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (c) 2023 Amlogic, Inc. All rights reserved.
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* Author: Chuan Liu <chuan.liu@amlogic.com>
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*/
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#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H
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#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H
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#define CLKID_RTC_XTAL_CLKIN 0
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#define CLKID_RTC_32K_DIV 1
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#define CLKID_RTC_32K_MUX 2
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#define CLKID_RTC_32K 3
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#define CLKID_RTC_CLK 4
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#define CLKID_SYS_RESET_CTRL 5
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#define CLKID_SYS_PWR_CTRL 6
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#define CLKID_SYS_PAD_CTRL 7
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#define CLKID_SYS_CTRL 8
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#define CLKID_SYS_TS_PLL 9
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#define CLKID_SYS_DEV_ARB 10
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#define CLKID_SYS_MMC_PCLK 11
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#define CLKID_SYS_CPU_CTRL 12
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#define CLKID_SYS_JTAG_CTRL 13
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#define CLKID_SYS_IR_CTRL 14
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#define CLKID_SYS_IRQ_CTRL 15
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#define CLKID_SYS_MSR_CLK 16
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#define CLKID_SYS_ROM 17
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#define CLKID_SYS_UART_F 18
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#define CLKID_SYS_CPU_ARB 19
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#define CLKID_SYS_RSA 20
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#define CLKID_SYS_SAR_ADC 21
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#define CLKID_SYS_STARTUP 22
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#define CLKID_SYS_SECURE 23
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#define CLKID_SYS_SPIFC 24
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#define CLKID_SYS_NNA 25
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#define CLKID_SYS_ETH_MAC 26
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#define CLKID_SYS_GIC 27
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#define CLKID_SYS_RAMA 28
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#define CLKID_SYS_BIG_NIC 29
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#define CLKID_SYS_RAMB 30
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#define CLKID_SYS_AUDIO_PCLK 31
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#define CLKID_SYS_PWM_KL 32
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#define CLKID_SYS_PWM_IJ 33
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#define CLKID_SYS_USB 34
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#define CLKID_SYS_SD_EMMC_A 35
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#define CLKID_SYS_SD_EMMC_C 36
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#define CLKID_SYS_PWM_AB 37
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#define CLKID_SYS_PWM_CD 38
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#define CLKID_SYS_PWM_EF 39
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#define CLKID_SYS_PWM_GH 40
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#define CLKID_SYS_SPICC_1 41
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#define CLKID_SYS_SPICC_0 42
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#define CLKID_SYS_UART_A 43
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#define CLKID_SYS_UART_B 44
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#define CLKID_SYS_UART_C 45
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#define CLKID_SYS_UART_D 46
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#define CLKID_SYS_UART_E 47
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#define CLKID_SYS_I2C_M_A 48
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#define CLKID_SYS_I2C_M_B 49
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#define CLKID_SYS_I2C_M_C 50
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#define CLKID_SYS_I2C_M_D 51
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#define CLKID_SYS_I2S_S_A 52
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#define CLKID_SYS_RTC 53
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#define CLKID_SYS_GE2D 54
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#define CLKID_SYS_ISP 55
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#define CLKID_SYS_GPV_ISP_NIC 56
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#define CLKID_SYS_GPV_CVE_NIC 57
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#define CLKID_SYS_MIPI_DSI_HOST 58
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#define CLKID_SYS_MIPI_DSI_PHY 59
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#define CLKID_SYS_ETH_PHY 60
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#define CLKID_SYS_ACODEC 61
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#define CLKID_SYS_DWAP 62
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#define CLKID_SYS_DOS 63
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#define CLKID_SYS_CVE 64
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#define CLKID_SYS_VOUT 65
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#define CLKID_SYS_VC9000E 66
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#define CLKID_SYS_PWM_MN 67
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#define CLKID_SYS_SD_EMMC_B 68
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#define CLKID_AXI_SYS_NIC 69
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#define CLKID_AXI_ISP_NIC 70
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#define CLKID_AXI_CVE_NIC 71
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#define CLKID_AXI_RAMB 72
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#define CLKID_AXI_RAMA 73
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#define CLKID_AXI_CPU_DMC 74
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#define CLKID_AXI_NIC 75
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#define CLKID_AXI_DMA 76
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#define CLKID_AXI_MUX_NIC 77
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#define CLKID_AXI_CVE 78
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#define CLKID_AXI_DEV1_DMC 79
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#define CLKID_AXI_DEV0_DMC 80
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#define CLKID_AXI_DSP_DMC 81
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#define CLKID_12_24M_IN 82
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#define CLKID_12M_24M 83
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#define CLKID_FCLK_25M_DIV 84
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#define CLKID_FCLK_25M 85
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#define CLKID_GEN_SEL 86
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#define CLKID_GEN_DIV 87
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#define CLKID_GEN 88
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#define CLKID_SARADC_SEL 89
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#define CLKID_SARADC_DIV 90
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#define CLKID_SARADC 91
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#define CLKID_PWM_A_SEL 92
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#define CLKID_PWM_A_DIV 93
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#define CLKID_PWM_A 94
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#define CLKID_PWM_B_SEL 95
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#define CLKID_PWM_B_DIV 96
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#define CLKID_PWM_B 97
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#define CLKID_PWM_C_SEL 98
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#define CLKID_PWM_C_DIV 99
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#define CLKID_PWM_C 100
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#define CLKID_PWM_D_SEL 101
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#define CLKID_PWM_D_DIV 102
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#define CLKID_PWM_D 103
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#define CLKID_PWM_E_SEL 104
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#define CLKID_PWM_E_DIV 105
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#define CLKID_PWM_E 106
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#define CLKID_PWM_F_SEL 107
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#define CLKID_PWM_F_DIV 108
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#define CLKID_PWM_F 109
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#define CLKID_PWM_G_SEL 110
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#define CLKID_PWM_G_DIV 111
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#define CLKID_PWM_G 112
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#define CLKID_PWM_H_SEL 113
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#define CLKID_PWM_H_DIV 114
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#define CLKID_PWM_H 115
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#define CLKID_PWM_I_SEL 116
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#define CLKID_PWM_I_DIV 117
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#define CLKID_PWM_I 118
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#define CLKID_PWM_J_SEL 119
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#define CLKID_PWM_J_DIV 120
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#define CLKID_PWM_J 121
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#define CLKID_PWM_K_SEL 122
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#define CLKID_PWM_K_DIV 123
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#define CLKID_PWM_K 124
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#define CLKID_PWM_L_SEL 125
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#define CLKID_PWM_L_DIV 126
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#define CLKID_PWM_L 127
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#define CLKID_PWM_M_SEL 128
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#define CLKID_PWM_M_DIV 129
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#define CLKID_PWM_M 130
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#define CLKID_PWM_N_SEL 131
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#define CLKID_PWM_N_DIV 132
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#define CLKID_PWM_N 133
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#define CLKID_SPICC_A_SEL 134
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#define CLKID_SPICC_A_DIV 135
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#define CLKID_SPICC_A 136
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#define CLKID_SPICC_B_SEL 137
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#define CLKID_SPICC_B_DIV 138
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#define CLKID_SPICC_B 139
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#define CLKID_SPIFC_SEL 140
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#define CLKID_SPIFC_DIV 141
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#define CLKID_SPIFC 142
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#define CLKID_SD_EMMC_A_SEL 143
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#define CLKID_SD_EMMC_A_DIV 144
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#define CLKID_SD_EMMC_A 145
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#define CLKID_SD_EMMC_B_SEL 146
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#define CLKID_SD_EMMC_B_DIV 147
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#define CLKID_SD_EMMC_B 148
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#define CLKID_SD_EMMC_C_SEL 149
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#define CLKID_SD_EMMC_C_DIV 150
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#define CLKID_SD_EMMC_C 151
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#define CLKID_TS_DIV 152
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#define CLKID_TS 153
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#define CLKID_ETH_125M_DIV 154
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#define CLKID_ETH_125M 155
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#define CLKID_ETH_RMII_DIV 156
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#define CLKID_ETH_RMII 157
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#define CLKID_MIPI_DSI_MEAS_SEL 158
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#define CLKID_MIPI_DSI_MEAS_DIV 159
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#define CLKID_MIPI_DSI_MEAS 160
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#define CLKID_DSI_PHY_SEL 161
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#define CLKID_DSI_PHY_DIV 162
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#define CLKID_DSI_PHY 163
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#define CLKID_VOUT_MCLK_SEL 164
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#define CLKID_VOUT_MCLK_DIV 165
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#define CLKID_VOUT_MCLK 166
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#define CLKID_VOUT_ENC_SEL 167
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#define CLKID_VOUT_ENC_DIV 168
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#define CLKID_VOUT_ENC 169
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#define CLKID_HCODEC_0_SEL 170
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#define CLKID_HCODEC_0_DIV 171
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#define CLKID_HCODEC_0 172
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#define CLKID_HCODEC_1_SEL 173
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#define CLKID_HCODEC_1_DIV 174
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#define CLKID_HCODEC_1 175
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#define CLKID_HCODEC 176
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#define CLKID_VC9000E_ACLK_SEL 177
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#define CLKID_VC9000E_ACLK_DIV 178
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#define CLKID_VC9000E_ACLK 179
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#define CLKID_VC9000E_CORE_SEL 180
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#define CLKID_VC9000E_CORE_DIV 181
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#define CLKID_VC9000E_CORE 182
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#define CLKID_CSI_PHY0_SEL 183
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#define CLKID_CSI_PHY0_DIV 184
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#define CLKID_CSI_PHY0 185
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#define CLKID_DEWARPA_SEL 186
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#define CLKID_DEWARPA_DIV 187
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#define CLKID_DEWARPA 188
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#define CLKID_ISP0_SEL 189
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#define CLKID_ISP0_DIV 190
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#define CLKID_ISP0 191
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#define CLKID_NNA_CORE_SEL 192
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#define CLKID_NNA_CORE_DIV 193
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#define CLKID_NNA_CORE 194
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#define CLKID_GE2D_SEL 195
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#define CLKID_GE2D_DIV 196
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#define CLKID_GE2D 197
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#define CLKID_VAPB_SEL 198
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#define CLKID_VAPB_DIV 199
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#define CLKID_VAPB 200
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#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H */
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