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LoongArch: Add architectural preparation for CPUFreq

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Add architectural preparation for CPUFreq driver, including: Kconfig,
register definition and platform device registration.

Some of LoongArch processors support DVFS, their IOCSR.FEATURES has
IOCSRF_FREQSCALE set. And they has a micro-core in the package called
SMC (System Management Controller) to scale frequency, voltage, etc.

Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This commit is contained in:
Huacai Chen 2024-07-20 22:41:06 +08:00
parent 8e02c3b782
commit f60d251b27
3 changed files with 19 additions and 0 deletions
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1
arch/loongarch/Kconfig
View File

@ -702,6 +702,7 @@ config ARCH_HIBERNATION_POSSIBLE
source "kernel/power/Kconfig"
source "drivers/acpi/Kconfig"
source "drivers/cpufreq/Kconfig"
endmenu

3
arch/loongarch/include/asm/loongarch.h
View File

@ -1061,11 +1061,14 @@
#define LOONGARCH_IOCSR_NODECNT 0x408
#define LOONGARCH_IOCSR_MISC_FUNC 0x420
#define IOCSR_MISC_FUNC_SOFT_INT BIT_ULL(10)
#define IOCSR_MISC_FUNC_TIMER_RESET BIT_ULL(21)
#define IOCSR_MISC_FUNC_EXT_IOI_EN BIT_ULL(48)
#define LOONGARCH_IOCSR_CPUTEMP 0x428
#define LOONGARCH_IOCSR_SMCMBX 0x51c
/* PerCore CSR, only accessible by local cores */
#define LOONGARCH_IOCSR_IPI_STATUS 0x1000
#define LOONGARCH_IOCSR_IPI_EN 0x1004

15
arch/loongarch/power/platform.c
View File

@ -34,6 +34,21 @@ void enable_pci_wakeup(void)
acpi_write_bit_register(ACPI_BITREG_PCIEXP_WAKE_DISABLE, 0);
}
static struct platform_device loongson3_cpufreq_device = {
.name = "loongson3_cpufreq",
.id = -1,
};
static int __init loongson_cpufreq_init(void)
{
if (!cpu_has_scalefreq)
return -ENODEV;
return platform_device_register(&loongson3_cpufreq_device);
}
arch_initcall(loongson_cpufreq_init);
static int __init loongson3_acpi_suspend_init(void)
{
#ifdef CONFIG_ACPI