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dmaengine: ipu: Remove the driver

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The i.MX3 IPU driver does not support devicetree and i.MX has been converted
to a DT-only platform since kernel 5.10.

As there is no user for this driver anymore, just remove it.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230729192945.1217206-1-festevam@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Fabio Estevam 2023-07-29 16:29:45 -03:00 committed by Vinod Koul
parent 1b13e52c0c
commit f1de55ff7c
6 changed files with 0 additions and 2363 deletions
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19
drivers/dma/Kconfig
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@ -472,25 +472,6 @@ config MXS_DMA
Support the MXS DMA engine. This engine including APBH-DMA
and APBX-DMA is integrated into some Freescale chips.
config MX3_IPU
bool "MX3x Image Processing Unit support"
depends on ARCH_MXC
select DMA_ENGINE
default y
help
If you plan to use the Image Processing unit in the i.MX3x, say
Y here. If unsure, select Y.
config MX3_IPU_IRQS
int "Number of dynamically mapped interrupts for IPU"
depends on MX3_IPU
range 2 137
default 4
help
Out of 137 interrupt sources on i.MX31 IPU only very few are used.
To avoid bloating the irq_desc[] array we allocate a sufficient
number of IRQ slots and map them dynamically to specific sources.
config NBPFAXI_DMA
tristate "Renesas Type-AXI NBPF DMA support"
select DMA_ENGINE

1
drivers/dma/Makefile
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@ -55,7 +55,6 @@ obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o
obj-$(CONFIG_MV_XOR) += mv_xor.o
obj-$(CONFIG_MV_XOR_V2) += mv_xor_v2.o
obj-$(CONFIG_MXS_DMA) += mxs-dma.o
obj-$(CONFIG_MX3_IPU) += ipu/
obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o
obj-$(CONFIG_OWL_DMA) += owl-dma.o
obj-$(CONFIG_PCH_DMA) += pch_dma.o

2
drivers/dma/ipu/Makefile
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@ -1,2 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y += ipu_irq.o ipu_idmac.o

1801
drivers/dma/ipu/ipu_idmac.c
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File diff suppressed because it is too large Load Diff

173
drivers/dma/ipu/ipu_intern.h
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@ -1,173 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2008
* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
*
* Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
#ifndef _IPU_INTERN_H_
#define _IPU_INTERN_H_
#include <linux/dmaengine.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
/* IPU Common registers */
#define IPU_CONF 0x00
#define IPU_CHA_BUF0_RDY 0x04
#define IPU_CHA_BUF1_RDY 0x08
#define IPU_CHA_DB_MODE_SEL 0x0C
#define IPU_CHA_CUR_BUF 0x10
#define IPU_FS_PROC_FLOW 0x14
#define IPU_FS_DISP_FLOW 0x18
#define IPU_TASKS_STAT 0x1C
#define IPU_IMA_ADDR 0x20
#define IPU_IMA_DATA 0x24
#define IPU_INT_CTRL_1 0x28
#define IPU_INT_CTRL_2 0x2C
#define IPU_INT_CTRL_3 0x30
#define IPU_INT_CTRL_4 0x34
#define IPU_INT_CTRL_5 0x38
#define IPU_INT_STAT_1 0x3C
#define IPU_INT_STAT_2 0x40
#define IPU_INT_STAT_3 0x44
#define IPU_INT_STAT_4 0x48
#define IPU_INT_STAT_5 0x4C
#define IPU_BRK_CTRL_1 0x50
#define IPU_BRK_CTRL_2 0x54
#define IPU_BRK_STAT 0x58
#define IPU_DIAGB_CTRL 0x5C
/* IPU_CONF Register bits */
#define IPU_CONF_CSI_EN 0x00000001
#define IPU_CONF_IC_EN 0x00000002
#define IPU_CONF_ROT_EN 0x00000004
#define IPU_CONF_PF_EN 0x00000008
#define IPU_CONF_SDC_EN 0x00000010
#define IPU_CONF_ADC_EN 0x00000020
#define IPU_CONF_DI_EN 0x00000040
#define IPU_CONF_DU_EN 0x00000080
#define IPU_CONF_PXL_ENDIAN 0x00000100
/* Image Converter Registers */
#define IC_CONF 0x88
#define IC_PRP_ENC_RSC 0x8C
#define IC_PRP_VF_RSC 0x90
#define IC_PP_RSC 0x94
#define IC_CMBP_1 0x98
#define IC_CMBP_2 0x9C
#define PF_CONF 0xA0
#define IDMAC_CONF 0xA4
#define IDMAC_CHA_EN 0xA8
#define IDMAC_CHA_PRI 0xAC
#define IDMAC_CHA_BUSY 0xB0
/* Image Converter Register bits */
#define IC_CONF_PRPENC_EN 0x00000001
#define IC_CONF_PRPENC_CSC1 0x00000002
#define IC_CONF_PRPENC_ROT_EN 0x00000004
#define IC_CONF_PRPVF_EN 0x00000100
#define IC_CONF_PRPVF_CSC1 0x00000200
#define IC_CONF_PRPVF_CSC2 0x00000400
#define IC_CONF_PRPVF_CMB 0x00000800
#define IC_CONF_PRPVF_ROT_EN 0x00001000
#define IC_CONF_PP_EN 0x00010000
#define IC_CONF_PP_CSC1 0x00020000
#define IC_CONF_PP_CSC2 0x00040000
#define IC_CONF_PP_CMB 0x00080000
#define IC_CONF_PP_ROT_EN 0x00100000
#define IC_CONF_IC_GLB_LOC_A 0x10000000
#define IC_CONF_KEY_COLOR_EN 0x20000000
#define IC_CONF_RWS_EN 0x40000000
#define IC_CONF_CSI_MEM_WR_EN 0x80000000
#define IDMA_CHAN_INVALID 0x000000FF
#define IDMA_IC_0 0x00000001
#define IDMA_IC_1 0x00000002
#define IDMA_IC_2 0x00000004
#define IDMA_IC_3 0x00000008
#define IDMA_IC_4 0x00000010
#define IDMA_IC_5 0x00000020
#define IDMA_IC_6 0x00000040
#define IDMA_IC_7 0x00000080
#define IDMA_IC_8 0x00000100
#define IDMA_IC_9 0x00000200
#define IDMA_IC_10 0x00000400
#define IDMA_IC_11 0x00000800
#define IDMA_IC_12 0x00001000
#define IDMA_IC_13 0x00002000
#define IDMA_SDC_BG 0x00004000
#define IDMA_SDC_FG 0x00008000
#define IDMA_SDC_MASK 0x00010000
#define IDMA_SDC_PARTIAL 0x00020000
#define IDMA_ADC_SYS1_WR 0x00040000
#define IDMA_ADC_SYS2_WR 0x00080000
#define IDMA_ADC_SYS1_CMD 0x00100000
#define IDMA_ADC_SYS2_CMD 0x00200000
#define IDMA_ADC_SYS1_RD 0x00400000
#define IDMA_ADC_SYS2_RD 0x00800000
#define IDMA_PF_QP 0x01000000
#define IDMA_PF_BSP 0x02000000
#define IDMA_PF_Y_IN 0x04000000
#define IDMA_PF_U_IN 0x08000000
#define IDMA_PF_V_IN 0x10000000
#define IDMA_PF_Y_OUT 0x20000000
#define IDMA_PF_U_OUT 0x40000000
#define IDMA_PF_V_OUT 0x80000000
#define TSTAT_PF_H264_PAUSE 0x00000001
#define TSTAT_CSI2MEM_MASK 0x0000000C
#define TSTAT_CSI2MEM_OFFSET 2
#define TSTAT_VF_MASK 0x00000600
#define TSTAT_VF_OFFSET 9
#define TSTAT_VF_ROT_MASK 0x000C0000
#define TSTAT_VF_ROT_OFFSET 18
#define TSTAT_ENC_MASK 0x00000180
#define TSTAT_ENC_OFFSET 7
#define TSTAT_ENC_ROT_MASK 0x00030000
#define TSTAT_ENC_ROT_OFFSET 16
#define TSTAT_PP_MASK 0x00001800
#define TSTAT_PP_OFFSET 11
#define TSTAT_PP_ROT_MASK 0x00300000
#define TSTAT_PP_ROT_OFFSET 20
#define TSTAT_PF_MASK 0x00C00000
#define TSTAT_PF_OFFSET 22
#define TSTAT_ADCSYS1_MASK 0x03000000
#define TSTAT_ADCSYS1_OFFSET 24
#define TSTAT_ADCSYS2_MASK 0x0C000000
#define TSTAT_ADCSYS2_OFFSET 26
#define TASK_STAT_IDLE 0
#define TASK_STAT_ACTIVE 1
#define TASK_STAT_WAIT4READY 2
struct idmac {
struct dma_device dma;
};
struct ipu {
void __iomem *reg_ipu;
void __iomem *reg_ic;
unsigned int irq_fn; /* IPU Function IRQ to the CPU */
unsigned int irq_err; /* IPU Error IRQ to the CPU */
unsigned int irq_base; /* Beginning of the IPU IRQ range */
unsigned long channel_init_mask;
spinlock_t lock;
struct clk *ipu_clk;
struct device *dev;
struct idmac idmac;
struct idmac_channel channel[IPU_CHANNELS_NUM];
struct tasklet_struct tasklet;
};
#define to_idmac(d) container_of(d, struct idmac, dma)
extern int ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev);
extern void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev);
extern bool ipu_irq_status(uint32_t irq);
extern int ipu_irq_map(unsigned int source);
extern int ipu_irq_unmap(unsigned int source);
#endif

367
drivers/dma/ipu/ipu_irq.c
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@ -1,367 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2008
* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
*/
#include <linux/init.h>
#include <linux/err.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/dma/ipu-dma.h>
#include "ipu_intern.h"
/*
* Register read / write - shall be inlined by the compiler
*/
static u32 ipu_read_reg(struct ipu *ipu, unsigned long reg)
{
return __raw_readl(ipu->reg_ipu + reg);
}
static void ipu_write_reg(struct ipu *ipu, u32 value, unsigned long reg)
{
__raw_writel(value, ipu->reg_ipu + reg);
}
/*
* IPU IRQ chip driver
*/
#define IPU_IRQ_NR_FN_BANKS 3
#define IPU_IRQ_NR_ERR_BANKS 2
#define IPU_IRQ_NR_BANKS (IPU_IRQ_NR_FN_BANKS + IPU_IRQ_NR_ERR_BANKS)
struct ipu_irq_bank {
unsigned int control;
unsigned int status;
struct ipu *ipu;
};
static struct ipu_irq_bank irq_bank[IPU_IRQ_NR_BANKS] = {
/* 3 groups of functional interrupts */
{
.control = IPU_INT_CTRL_1,
.status = IPU_INT_STAT_1,
}, {
.control = IPU_INT_CTRL_2,
.status = IPU_INT_STAT_2,
}, {
.control = IPU_INT_CTRL_3,
.status = IPU_INT_STAT_3,
},
/* 2 groups of error interrupts */
{
.control = IPU_INT_CTRL_4,
.status = IPU_INT_STAT_4,
}, {
.control = IPU_INT_CTRL_5,
.status = IPU_INT_STAT_5,
},
};
struct ipu_irq_map {
unsigned int irq;
int source;
struct ipu_irq_bank *bank;
struct ipu *ipu;
};
static struct ipu_irq_map irq_map[CONFIG_MX3_IPU_IRQS];
/* Protects allocations from the above array of maps */
static DEFINE_MUTEX(map_lock);
/* Protects register accesses and individual mappings */
static DEFINE_RAW_SPINLOCK(bank_lock);
static struct ipu_irq_map *src2map(unsigned int src)
{
int i;
for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++)
if (irq_map[i].source == src)
return irq_map + i;
return NULL;
}
static void ipu_irq_unmask(struct irq_data *d)
{
struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
struct ipu_irq_bank *bank;
uint32_t reg;
unsigned long lock_flags;
raw_spin_lock_irqsave(&bank_lock, lock_flags);
bank = map->bank;
if (!bank) {
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
return;
}
reg = ipu_read_reg(bank->ipu, bank->control);
reg |= (1UL << (map->source & 31));
ipu_write_reg(bank->ipu, reg, bank->control);
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
}
static void ipu_irq_mask(struct irq_data *d)
{
struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
struct ipu_irq_bank *bank;
uint32_t reg;
unsigned long lock_flags;
raw_spin_lock_irqsave(&bank_lock, lock_flags);
bank = map->bank;
if (!bank) {
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
return;
}
reg = ipu_read_reg(bank->ipu, bank->control);
reg &= ~(1UL << (map->source & 31));
ipu_write_reg(bank->ipu, reg, bank->control);
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
}
static void ipu_irq_ack(struct irq_data *d)
{
struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
struct ipu_irq_bank *bank;
unsigned long lock_flags;
raw_spin_lock_irqsave(&bank_lock, lock_flags);
bank = map->bank;
if (!bank) {
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
return;
}
ipu_write_reg(bank->ipu, 1UL << (map->source & 31), bank->status);
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
}
/**
* ipu_irq_status() - returns the current interrupt status of the specified IRQ.
* @irq: interrupt line to get status for.
* @return: true if the interrupt is pending/asserted or false if the
* interrupt is not pending.
*/
bool ipu_irq_status(unsigned int irq)
{
struct ipu_irq_map *map = irq_get_chip_data(irq);
struct ipu_irq_bank *bank;
unsigned long lock_flags;
bool ret;
raw_spin_lock_irqsave(&bank_lock, lock_flags);
bank = map->bank;
ret = bank && ipu_read_reg(bank->ipu, bank->status) &
(1UL << (map->source & 31));
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
return ret;
}
/**
* ipu_irq_map() - map an IPU interrupt source to an IRQ number
* @source: interrupt source bit position (see below)
* @return: mapped IRQ number or negative error code
*
* The source parameter has to be explained further. On i.MX31 IPU has 137 IRQ
* sources, they are broken down in 5 32-bit registers, like 32, 32, 24, 32, 17.
* However, the source argument of this function is not the sequence number of
* the possible IRQ, but rather its bit position. So, first interrupt in fourth
* register has source number 96, and not 88. This makes calculations easier,
* and also provides forward compatibility with any future IPU implementations
* with any interrupt bit assignments.
*/
int ipu_irq_map(unsigned int source)
{
int i, ret = -ENOMEM;
struct ipu_irq_map *map;
might_sleep();
mutex_lock(&map_lock);
map = src2map(source);
if (map) {
pr_err("IPU: Source %u already mapped to IRQ %u\n", source, map->irq);
ret = -EBUSY;
goto out;
}
for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
if (irq_map[i].source < 0) {
unsigned long lock_flags;
raw_spin_lock_irqsave(&bank_lock, lock_flags);
irq_map[i].source = source;
irq_map[i].bank = irq_bank + source / 32;
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
ret = irq_map[i].irq;
pr_debug("IPU: mapped source %u to IRQ %u\n",
source, ret);
break;
}
}
out:
mutex_unlock(&map_lock);
if (ret < 0)
pr_err("IPU: couldn't map source %u: %d\n", source, ret);
return ret;
}
/**
* ipu_irq_unmap() - unmap an IPU interrupt source
* @source: interrupt source bit position (see ipu_irq_map())
* @return: 0 or negative error code
*/
int ipu_irq_unmap(unsigned int source)
{
int i, ret = -EINVAL;
might_sleep();
mutex_lock(&map_lock);
for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
if (irq_map[i].source == source) {
unsigned long lock_flags;
pr_debug("IPU: unmapped source %u from IRQ %u\n",
source, irq_map[i].irq);
raw_spin_lock_irqsave(&bank_lock, lock_flags);
irq_map[i].source = -EINVAL;
irq_map[i].bank = NULL;
raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
ret = 0;
break;
}
}
mutex_unlock(&map_lock);
return ret;
}
/* Chained IRQ handler for IPU function and error interrupt */
static void ipu_irq_handler(struct irq_desc *desc)
{
struct ipu *ipu = irq_desc_get_handler_data(desc);
u32 status;
int i, line;
for (i = 0; i < IPU_IRQ_NR_BANKS; i++) {
struct ipu_irq_bank *bank = irq_bank + i;
raw_spin_lock(&bank_lock);
status = ipu_read_reg(ipu, bank->status);
/*
* Don't think we have to clear all interrupts here, they will
* be acked by ->handle_irq() (handle_level_irq). However, we
* might want to clear unhandled interrupts after the loop...
*/
status &= ipu_read_reg(ipu, bank->control);
raw_spin_unlock(&bank_lock);
while ((line = ffs(status))) {
struct ipu_irq_map *map;
unsigned int irq;
line--;
status &= ~(1UL << line);
raw_spin_lock(&bank_lock);
map = src2map(32 * i + line);
if (!map) {
raw_spin_unlock(&bank_lock);
pr_err("IPU: Interrupt on unmapped source %u bank %d\n",
line, i);
continue;
}
irq = map->irq;
raw_spin_unlock(&bank_lock);
generic_handle_irq(irq);
}
}
}
static struct irq_chip ipu_irq_chip = {
.name = "ipu_irq",
.irq_ack = ipu_irq_ack,
.irq_mask = ipu_irq_mask,
.irq_unmask = ipu_irq_unmask,
};
/* Install the IRQ handler */
int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
{
unsigned int irq, i;
int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS,
numa_node_id());
if (irq_base < 0)
return irq_base;
for (i = 0; i < IPU_IRQ_NR_BANKS; i++)
irq_bank[i].ipu = ipu;
for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
int ret;
irq = irq_base + i;
ret = irq_set_chip(irq, &ipu_irq_chip);
if (ret < 0)
return ret;
ret = irq_set_chip_data(irq, irq_map + i);
if (ret < 0)
return ret;
irq_map[i].ipu = ipu;
irq_map[i].irq = irq;
irq_map[i].source = -EINVAL;
irq_set_handler(irq, handle_level_irq);
irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
}
irq_set_chained_handler_and_data(ipu->irq_fn, ipu_irq_handler, ipu);
irq_set_chained_handler_and_data(ipu->irq_err, ipu_irq_handler, ipu);
ipu->irq_base = irq_base;
return 0;
}
void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev)
{
unsigned int irq, irq_base;
irq_base = ipu->irq_base;
irq_set_chained_handler_and_data(ipu->irq_fn, NULL, NULL);
irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
for (irq = irq_base; irq < irq_base + CONFIG_MX3_IPU_IRQS; irq++) {
irq_set_status_flags(irq, IRQ_NOREQUEST);
irq_set_chip(irq, NULL);
irq_set_chip_data(irq, NULL);
}
}