kevin/linux
1
Fork 0
Code

iommu/amd: Add kernel parameters to limit V1 page-sizes

Browse Source 
Add two new kernel command line parameters to limit the page-sizes
used for v1 page-tables:

	nohugepages     - Limits page-sizes to 4KiB

	v2_pgsizes_only - Limits page-sizes to 4Kib/2Mib/1GiB; The
	                  same as the sizes used with v2 page-tables

This is needed for multiple scenarios. When assigning devices to
SEV-SNP guests the IOMMU page-sizes need to match the sizes in the RMP
table, otherwise the device will not be able to access all shared
memory.

Also, some ATS devices do not work properly with arbitrary IO
page-sizes as supported by AMD-Vi, so limiting the sizes used by the
driver is a suitable workaround.

All-in-all, these parameters are only workarounds until the IOMMU core
and related APIs gather the ability to negotiate the page-sizes in a
better way.

Signed-off-by: Joerg Roedel <jroedel@suse.de>
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
Link: https://lore.kernel.org/r/20240905072240.253313-1-joro@8bytes.org
This commit is contained in:
Joerg Roedel 2024-09-05 09:22:40 +02:00
parent 2910a7fa1b
commit f0295913c4
5 changed files with 25 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
Documentation/admin-guide/kernel-parameters.txt
View File

@ -333,12 +333,17 @@
allowed anymore to lift isolation allowed anymore to lift isolation
requirements as needed. This option requirements as needed. This option
does not override iommu=pt does not override iommu=pt
force_enable - Force enable the IOMMU on platforms known force_enable - Force enable the IOMMU on platforms known
to be buggy with IOMMU enabled. Use this to be buggy with IOMMU enabled. Use this
option with care. option with care.
pgtbl_v1 - Use v1 page table for DMA-API (Default). pgtbl_v1 - Use v1 page table for DMA-API (Default).
pgtbl_v2 - Use v2 page table for DMA-API. pgtbl_v2 - Use v2 page table for DMA-API.
irtcachedis - Disable Interrupt Remapping Table (IRT) caching. irtcachedis - Disable Interrupt Remapping Table (IRT) caching.
nohugepages - Limit page-sizes used for v1 page-tables
to 4 KiB.
v2_pgsizes_only - Limit page-sizes used for v1 page-tables
to 4KiB/2Mib/1GiB.
amd_iommu_dump= [HW,X86-64] amd_iommu_dump= [HW,X86-64]
Enable AMD IOMMU driver option to dump the ACPI table Enable AMD IOMMU driver option to dump the ACPI table

1
drivers/iommu/amd/amd_iommu.h
View File

@ -43,6 +43,7 @@ int amd_iommu_enable_faulting(unsigned int cpu);
extern int amd_iommu_guest_ir; extern int amd_iommu_guest_ir;
extern enum io_pgtable_fmt amd_iommu_pgtable; extern enum io_pgtable_fmt amd_iommu_pgtable;
extern int amd_iommu_gpt_level; extern int amd_iommu_gpt_level;
extern unsigned long amd_iommu_pgsize_bitmap;
/* Protection domain ops */ /* Protection domain ops */
struct protection_domain *protection_domain_alloc(unsigned int type, int nid); struct protection_domain *protection_domain_alloc(unsigned int type, int nid);

4
drivers/iommu/amd/amd_iommu_types.h
View File

@ -293,6 +293,10 @@
* Page sizes >= the 52 bit max physical address of the CPU are not supported. * Page sizes >= the 52 bit max physical address of the CPU are not supported.
*/ */
#define AMD_IOMMU_PGSIZES (GENMASK_ULL(51, 12) ^ SZ_512G) #define AMD_IOMMU_PGSIZES (GENMASK_ULL(51, 12) ^ SZ_512G)
/* Special mode where page-sizes are limited to 4 KiB */
#define AMD_IOMMU_PGSIZES_4K (PAGE_SIZE)
/* 4K, 2MB, 1G page sizes are supported */ /* 4K, 2MB, 1G page sizes are supported */
#define AMD_IOMMU_PGSIZES_V2 (PAGE_SIZE | (1ULL << 21) | (1ULL << 30)) #define AMD_IOMMU_PGSIZES_V2 (PAGE_SIZE | (1ULL << 21) | (1ULL << 30))

8
drivers/iommu/amd/init.c
View File

@ -192,6 +192,8 @@ bool amdr_ivrs_remap_support __read_mostly;
bool amd_iommu_force_isolation __read_mostly; bool amd_iommu_force_isolation __read_mostly;
unsigned long amd_iommu_pgsize_bitmap __ro_after_init = AMD_IOMMU_PGSIZES;
/* /*
* AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
* to know which ones are already in use. * to know which ones are already in use.
@ -3492,6 +3494,12 @@ static int __init parse_amd_iommu_options(char *str)
amd_iommu_pgtable = AMD_IOMMU_V2; amd_iommu_pgtable = AMD_IOMMU_V2;
} else if (strncmp(str, "irtcachedis", 11) == 0) { } else if (strncmp(str, "irtcachedis", 11) == 0) {
amd_iommu_irtcachedis = true; amd_iommu_irtcachedis = true;
} else if (strncmp(str, "nohugepages", 11) == 0) {
pr_info("Restricting V1 page-sizes to 4KiB");
amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_4K;
} else if (strncmp(str, "v2_pgsizes_only", 15) == 0) {
pr_info("Restricting V1 page-sizes to 4KiB/2MiB/1GiB");
amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_V2;
} else { } else {
pr_notice("Unknown option - '%s'\n", str); pr_notice("Unknown option - '%s'\n", str);
} }

2
drivers/iommu/amd/io_pgtable.c
View File

@ -548,7 +548,7 @@ static struct io_pgtable *v1_alloc_pgtable(struct io_pgtable_cfg *cfg, void *coo
return NULL; return NULL;
pgtable->mode = PAGE_MODE_3_LEVEL; pgtable->mode = PAGE_MODE_3_LEVEL;
cfg->pgsize_bitmap = AMD_IOMMU_PGSIZES; cfg->pgsize_bitmap = amd_iommu_pgsize_bitmap;
cfg->ias = IOMMU_IN_ADDR_BIT_SIZE; cfg->ias = IOMMU_IN_ADDR_BIT_SIZE;
cfg->oas = IOMMU_OUT_ADDR_BIT_SIZE; cfg->oas = IOMMU_OUT_ADDR_BIT_SIZE;