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STM32 DT for v6.9, round 1

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Highlights:
 ----------
 
 - MCU:
   - Add DSI support on stm32f769.
   - Add display support on stm32f769-disco.
   - Add stm32f769-disco-mb1166-reva09 board support which belongs to
     the novatek NT35510 panel.
 
 - MPU:
   - STM32MP13:
     - Add CRC support an enable it on stm32mp135f-dk.
     - Enable CRYP on stm32mp135f-dk.
 
   - STMP32MP15:
    - Fix DSI peripheral clock: use bus clock instead of kernel clock
      for pclk.
 
    - LXA: driver powerboard lines as open drain.
    - LXA: reduce RGMII drive strenght to reduce EMI emmissions.
 
   - STM32MP25:
     - Add video encoder / video decoder support.
 -----BEGIN PGP SIGNATURE-----
 
 iQJRBAABCgA7FiEEctl9+nxzUSUqdELdf5rJavIecIUFAmXgVQ8dHGFsZXhhbmRy
 ZS50b3JndWVAZm9zcy5zdC5jb20ACgkQf5rJavIecIXNVA/+PqcJRmO1aWmj/1HY
 DSwmCZ9W8kIVuUT1X/oAcb2UwiDOvNNSelAKARs4KWmc54sH7LW7xek7iEes127a
 xaqdnCShFdHYtqfrVsiPTncRjplNzKrvINvKDdkPvFHp0qgQ7IjwWlkZY2JOssya
 9iorKAu846fxD8/1QJUDmnJOpXY4lvl4XczMICw5NKEAV5L6oIf4jiND59h/jd0d
 5vYO99wy5f4Gf0uSJSgGPDJxtyJwjff2HaNZJGL5dHstd7VF8gUV/Nvd6rMhaAEv
 dpkITRnmS7aF3+BBXDM3pa8zVuXwnNd/6w5OWSUJNRL+LQEmeS3aUSJ3BxrsGXtL
 75drVHdLhqHtxYrEJlRSWnAUNJMrG/SDN6nfcTPV5F0Mlj8B790K6E9c5YA5iYAH
 9yeGaOPj3EcTo2nzfvZMdpuO6Dw0wn3ahzGjBWg24F4QfSqKvfuok0A6FgXQEKvj
 b98HLiywy3hBZGnupxHzGRFp+LO41o1uVzCMMoSZoXSNH0JIm/3de3lFcpmxlkmG
 p0/+5scL1f3Jfc9x4D6Xa7pwZOrfZiZ8JM8DOCVEO2LQ5d/p0mcR4zMLVCYS8LQA
 6GQseDUR+egEpRpnejIPvWm06CSKBm5PuZLByWPKmkEXMMPQM07wQfMeyIwWJ/cO
 MGwMoAU2qaerBYlhSb87d2eFJ44=
 =CSVX
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXlblUACgkQYKtH/8kJ
 UieUzw//VkCNYTje/5+dZ19wa9Rw5upL9awkgKvIfzs7lwmVivPRVUHoCpGNSsNc
 AFHc+AdLFynwowShOR4oMDyT4f50b4+1OXfUXIRI6vDkg42vbqBoMrYrSFqtMJRt
 RbRaMRm9QrInHzoQzJgKIvq+Jo57TCXuEeE7tPMVhR48h2yB8rlwkP74oEnvVFgl
 iLtU9ScXZe0dS/inBadKF7tSv57I7FTFMCQ5wSqvwPF3QAT21EaXdp5daE0Vf71f
 r1Jgy1AAm4JWrMexAtDJCuSx2stYMK7n8VKZBB6AZ4321TFlrIGnY4GGVU5vJXRS
 X2sfWKK/YHucfSC1w+Mwr8pVGicjZy+4izNDyqDcTivkSohLDsf74UDNZqjzs0gT
 yvzH1MwIqKHgkcjWo5ZP/Sf2M8DU8L65IwFn9Yf5l7LaEIT9ZZGGLDgosz4gTR2b
 aRiz5g1S2gsodJgsFQhFFebjtI5cxmnZC9rRxdDMT8KHS8RE2h7WuJt102NkFKNO
 pReg5RPEcJ6JYoQk/4lBN6L4ls5o8txu1YMeS9uxq5kt8tiejz1ZzT97FfD+yWBg
 sizT6AW+FojLsWiSeRUtsTjvzfkI0/gCGx8AorzG8nWJCDWSq1qIxUoucqTk0naM
 vTQDLi4Lf6g2USSwl/cXaaTOVJ8QYVzCbwqwDjgNceReP9FEpkE=
 =p/sn
 -----END PGP SIGNATURE-----

Merge tag 'stm32-dt-for-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt

STM32 DT for v6.9, round 1

Highlights:
----------

- MCU:
  - Add DSI support on stm32f769.
  - Add display support on stm32f769-disco.
  - Add stm32f769-disco-mb1166-reva09 board support which belongs to
    the novatek NT35510 panel.

- MPU:
  - STM32MP13:
    - Add CRC support an enable it on stm32mp135f-dk.
    - Enable CRYP on stm32mp135f-dk.

  - STMP32MP15:
   - Fix DSI peripheral clock: use bus clock instead of kernel clock
     for pclk.

   - LXA: driver powerboard lines as open drain.
   - LXA: reduce RGMII drive strenght to reduce EMI emmissions.

  - STM32MP25:
    - Add video encoder / video decoder support.

* tag 'stm32-dt-for-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  arm64: dts: st: add video encoder support to stm32mp255
  arm64: dts: st: add video decoder support to stm32mp255
  ARM: dts: stm32: enable crypto accelerator on stm32mp135f-dk
  ARM: dts: stm32: enable CRC on stm32mp135f-dk
  ARM: dts: stm32: add CRC on stm32mp131
  ARM: dts: add stm32f769-disco-mb1166-reva09
  ARM: dts: stm32: add display support on stm32f769-disco
  ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f769-disco
  ARM: dts: stm32: add DSI support on stm32f769
  dt-bindings: mfd: stm32f7: Add binding definition for DSI
  dt-bindings: nt35510: document 'port' property
  ARM: dts: stm32: lxa-tac: reduce RGMII interface drive strength
  ARM: dts: stm32: fix DSI peripheral clock on stm32mp15 boards
  ARM: dts: stm32: lxa-tac: drive powerboard lines as open-drain

Link: https://lore.kernel.org/r/a7ae1058-e24d-4a6b-900f-401f0e3ae17c@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-03-04 07:46:39 +01:00
commit f011770485
17 changed files with 157 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml
View File

@ -29,6 +29,7 @@ properties:
vddi-supply:
description: regulator that supplies the vddi voltage
backlight: true
port: true
required:
- compatible

1
arch/arm/boot/dts/st/Makefile
View File

@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32f469-disco.dtb \
stm32f746-disco.dtb \
stm32f769-disco.dtb \
stm32f769-disco-mb1166-reva09.dtb \
stm32429i-eval.dtb \
stm32746g-eval.dtb \
stm32h743i-eval.dtb \

13
arch/arm/boot/dts/st/stm32f769-disco-mb1166-reva09.dts Normal file
View File

@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com>
*/
#include "stm32f769-disco.dts"
&panel0 {
compatible = "frida,frd400b25025", "novatek,nt35510";
vddi-supply = <&vcc_3v3>;
vdd-supply = <&vcc_3v3>;
/delete-property/power-supply;
};

70
arch/arm/boot/dts/st/stm32f769-disco.dts
View File

@ -41,7 +41,7 @@
*/
/dts-v1/;
#include "stm32f746.dtsi"
#include "stm32f769.dtsi"
#include "stm32f769-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
@ -60,6 +60,19 @@
reg = <0xC0000000 0x1000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
linux,dma {
compatible = "shared-dma-pool";
linux,dma-default;
no-map;
size = <0x100000>;
};
};
aliases {
serial0 = &usart1;
};
@ -92,9 +105,9 @@
clock-names = "main_clk";
};
mmc_vcard: mmc_vcard {
vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "mmc_vcard";
regulator-name = "vcc_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
@ -114,6 +127,45 @@
clock-frequency = <25000000>;
};
&dsi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
remote-endpoint = <&ltdc_out_dsi>;
};
};
port@1 {
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&dsi_panel_in>;
};
};
};
panel0: panel@0 {
compatible = "orisetech,otm8009a";
reg = <0>; /* dsi virtual channel (0..3) */
reset-gpios = <&gpioj 15 GPIO_ACTIVE_LOW>;
power-supply = <&vcc_3v3>;
status = "okay";
port {
dsi_panel_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins_b>;
pinctrl-names = "default";
@ -122,13 +174,23 @@
status = "okay";
};
&ltdc {
status = "okay";
port {
ltdc_out_dsi: endpoint {
remote-endpoint = <&dsi_in>;
};
};
};
&rtc {
status = "okay";
};
&sdio2 {
status = "okay";
vmmc-supply = <&mmc_vcard>;
vmmc-supply = <&vcc_3v3>;
cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
broken-cd;
pinctrl-names = "default", "opendrain", "sleep";

20
arch/arm/boot/dts/st/stm32f769.dtsi Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com>
*/
#include "stm32f746.dtsi"
/ {
soc {
dsi: dsi@40016c00 {
compatible = "st,stm32-dsi";
reg = <0x40016c00 0x800>;
clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>;
clock-names = "pclk", "ref";
resets = <&rcc STM32F7_APB2_RESET(DSI)>;
reset-names = "apb";
status = "disabled";
};
};
};

7
arch/arm/boot/dts/st/stm32mp131.dtsi
View File

@ -1315,6 +1315,13 @@
status = "disabled";
};
crc1: crc@58009000 {
compatible = "st,stm32f7-crc";
reg = <0x58009000 0x400>;
clocks = <&rcc CRC1>;
status = "disabled";
};
usbh_ohci: usb@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;

8
arch/arm/boot/dts/st/stm32mp135f-dk.dts
View File

@ -93,6 +93,14 @@
};
};
&crc1 {
status = "okay";
};
&cryp {
status = "okay";
};
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;

2
arch/arm/boot/dts/st/stm32mp157.dtsi
View File

@ -20,7 +20,7 @@
dsi: dsi@5a000000 {
compatible = "st,stm32-dsi";
reg = <0x5a000000 0x800>;
clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>;
clock-names = "pclk", "ref", "px_clk";
phy-dsi-supply = <&reg18>;
resets = <&rcc DSI_R>;

2
arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
View File

@ -30,7 +30,7 @@
};
&dsi {
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {

2
arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
View File

@ -36,7 +36,7 @@
&dsi {
phy-dsi-supply = <&scmi_reg18>;
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {

2
arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
View File

@ -35,7 +35,7 @@
};
&dsi {
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {

2
arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
View File

@ -36,7 +36,7 @@
&dsi {
phy-dsi-supply = <&scmi_reg18>;
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {

2
arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts
View File

@ -148,7 +148,7 @@
compatible = "ti,lmp92064";
reg = <0>;
reset-gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
shunt-resistor-micro-ohms = <15000>;
spi-max-frequency = <5000000>;
vdd-supply = <&reg_pb_3v3>;

6
arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi
View File

@ -409,7 +409,7 @@ baseboard_eeprom: &sip_eeprom {
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_c>;
cs-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpiof 12 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@ -471,6 +471,10 @@ baseboard_eeprom: &sip_eeprom {
interrupt-parent = <&gpioa>;
interrupts = <6 IRQ_TYPE_EDGE_RISING>;
/* Reduce RGMII EMI emissions by reducing drive strength */
microchip,hi-drive-strength-microamp = <2000>;
microchip,lo-drive-strength-microamp = <8000>;
ports {
#address-cells = <1>;
#size-cells = <0>;

12
arch/arm64/boot/dts/st/stm32mp251.dtsi
View File

@ -52,6 +52,18 @@
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
ck_icn_p_vdec: ck-icn-p-vdec {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
ck_icn_p_venc: ck-icn-p-venc {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
};
firmware {

17
arch/arm64/boot/dts/st/stm32mp255.dtsi
View File

@ -6,4 +6,21 @@
#include "stm32mp253.dtsi"
/ {
soc@0 {
rifsc: rifsc-bus@42080000 {
vdec: vdec@480d0000 {
compatible = "st,stm32mp25-vdec";
reg = <0x480d0000 0x3c8>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ck_icn_p_vdec>;
};
venc: venc@480e0000 {
compatible = "st,stm32mp25-venc";
reg = <0x480e0000 0x800>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ck_icn_ls_mcu>;
};
};
};
};

1
include/dt-bindings/mfd/stm32f7-rcc.h
View File

@ -108,6 +108,7 @@
#define STM32F7_RCC_APB2_SAI1 22
#define STM32F7_RCC_APB2_SAI2 23
#define STM32F7_RCC_APB2_LTDC 26
#define STM32F7_RCC_APB2_DSI 27
#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8))
#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)