scsi: pm8001: Remove PM8001_USE_MSIX
The pm8001 driver does not compile if PM8001_USE_MSIX is not defined in pm8001_sas.h because various fields and functions conditionally defined are used unconditionally without a "#ifdef PM8001_USE_MSIX" protection. This macro is rather useless anyway and not convenient as diabling MSI-X use requires recompiling the driver. Remove this macro and replace it with the bool module parameter "use_msix" which defaults to true. The use of MSI-X interrupts for an adapter is gated by this module parameter for adapters that actually support MSI-X. The "use_msix" boolean field is added to struct pm8001_hba_info and all code defined depending on PM8001_USE_MSIX is modified to rely on pm8001_hba_info->use_msix instead. Signed-off-by: Damien Le Moal <dlemoal@kernel.org> Link: https://lore.kernel.org/r/20230911232745.325149-9-dlemoal@kernel.org Acked-by: Jack Wang <jinpu.wang@ionos.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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@ -1188,13 +1188,14 @@ void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
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static void
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pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
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{
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#ifdef PM8001_USE_MSIX
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pm8001_cw32(pm8001_ha, 0, MSIX_TABLE_BASE, MSIX_INTERRUPT_ENABLE);
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if (pm8001_ha->use_msix) {
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pm8001_cw32(pm8001_ha, 0, MSIX_TABLE_BASE,
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MSIX_INTERRUPT_ENABLE);
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pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, 1);
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#else
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} else {
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
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pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
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#endif
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}
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}
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/**
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@ -1205,11 +1206,11 @@ pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
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static void
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pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
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{
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#ifdef PM8001_USE_MSIX
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pm8001_cw32(pm8001_ha, 0, MSIX_TABLE_BASE, MSIX_INTERRUPT_DISABLE);
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#else
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if (pm8001_ha->use_msix)
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pm8001_cw32(pm8001_ha, 0, MSIX_TABLE_BASE,
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MSIX_INTERRUPT_DISABLE);
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else
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
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#endif
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}
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/**
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@ -4252,16 +4253,15 @@ static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
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static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
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{
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#ifdef PM8001_USE_MSIX
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return 1;
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#else
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u32 value;
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if (pm8001_ha->use_msix)
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return 1;
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value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
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if (value)
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return 1;
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return 0;
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#endif
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}
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/**
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@ -56,6 +56,10 @@ MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
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" 4: Link rate 6.0G\n"
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" 8: Link rate 12.0G\n");
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bool pm8001_use_msix = true;
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module_param_named(use_msix, pm8001_use_msix, bool, 0444);
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MODULE_PARM_DESC(zoned, "Use MSIX interrupts. Default: true");
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static struct scsi_transport_template *pm8001_stt;
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static int pm8001_init_ccb_tag(struct pm8001_hba_info *);
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@ -961,7 +965,6 @@ static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
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}
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}
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#ifdef PM8001_USE_MSIX
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/**
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* pm8001_setup_msix - enable MSI-X interrupt
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* @pm8001_ha: our ha struct.
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@ -1043,7 +1046,6 @@ static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
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return rc;
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}
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#endif
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/**
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* pm8001_request_irq - register interrupt
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@ -1052,10 +1054,9 @@ static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
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static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
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{
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struct pci_dev *pdev = pm8001_ha->pdev;
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#ifdef PM8001_USE_MSIX
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int rc;
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if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) {
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if (pm8001_use_msix && pci_find_capability(pdev, PCI_CAP_ID_MSIX)) {
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rc = pm8001_setup_msix(pm8001_ha);
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if (rc) {
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pm8001_dbg(pm8001_ha, FAIL,
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@ -1063,14 +1064,22 @@ static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
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return rc;
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}
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if (pdev->msix_cap && pci_msi_enabled())
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return pm8001_request_msix(pm8001_ha);
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if (!pdev->msix_cap || !pci_msi_enabled())
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goto use_intx;
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rc = pm8001_request_msix(pm8001_ha);
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if (rc)
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return rc;
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pm8001_ha->use_msix = true;
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return 0;
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}
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use_intx:
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/* Initialize the INT-X interrupt */
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pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
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#endif
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/* initialize the INT-X interrupt */
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pm8001_ha->use_msix = false;
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pm8001_ha->irq_vector[0].irq_id = 0;
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pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
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@ -1081,10 +1090,10 @@ static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
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static void pm8001_free_irq(struct pm8001_hba_info *pm8001_ha)
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{
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#ifdef PM8001_USE_MSIX
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struct pci_dev *pdev = pm8001_ha->pdev;
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int i;
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if (pm8001_ha->use_msix) {
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for (i = 0; i < pm8001_ha->number_of_intr; i++)
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synchronize_irq(pci_irq_vector(pdev, i));
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@ -1092,9 +1101,11 @@ static void pm8001_free_irq(struct pm8001_hba_info *pm8001_ha)
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free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
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pci_free_irq_vectors(pdev);
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#else
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return;
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}
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/* INT-X */
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free_irq(pm8001_ha->irq, pm8001_ha->sas);
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#endif
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}
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/**
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@ -83,8 +83,9 @@ do { \
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pm8001_info(HBA, fmt, ##__VA_ARGS__); \
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} while (0)
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extern bool pm8001_use_msix;
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#define PM8001_USE_TASKLET
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#define PM8001_USE_MSIX
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#define PM8001_READ_VPD
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@ -520,11 +521,11 @@ struct pm8001_hba_info {
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struct pm8001_device *devices;
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struct pm8001_ccb_info *ccb_info;
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u32 ccb_count;
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#ifdef PM8001_USE_MSIX
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bool use_msix;
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int number_of_intr;/*will be used in remove()*/
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char intr_drvname[PM8001_MAX_MSIX_VEC]
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[PM8001_NAME_LENGTH+1+3+1];
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#endif
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#ifdef PM8001_USE_TASKLET
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struct tasklet_struct tasklet[PM8001_MAX_MSIX_VEC];
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#endif
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@ -1722,16 +1722,16 @@ static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
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static void
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pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
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{
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#ifdef PM8001_USE_MSIX
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if (!pm8001_ha->use_msix) {
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
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pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
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return;
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}
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if (vec < 32)
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
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else
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,
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1U << (vec - 32));
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#else
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
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pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
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#endif
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U, 1U << (vec - 32));
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}
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/**
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@ -1742,19 +1742,20 @@ pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
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static void
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pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
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{
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#ifdef PM8001_USE_MSIX
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if (!pm8001_ha->use_msix) {
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
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return;
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}
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if (vec == 0xFF) {
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/* disable all vectors 0-31, 32-63 */
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
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} else if (vec < 32)
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} else if (vec < 32) {
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
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else
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,
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1U << (vec - 32));
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#else
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
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#endif
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} else {
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pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 1U << (vec - 32));
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}
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}
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/**
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@ -4781,16 +4782,15 @@ static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
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static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
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{
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#ifdef PM8001_USE_MSIX
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return 1;
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#else
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u32 value;
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if (pm8001_ha->use_msix)
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return 1;
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value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
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if (value)
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return 1;
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return 0;
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#endif
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}
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/**
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