arm: vexpress: Remove obsolete RTSM DCSCB support
The Arm Versatile DCSCB support is unused as the compatible "arm,rtsm,dcscb" is unused in any .dts file. It was only ever implemented on a s/w model (RTSM). Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20240510123238.3904779-1-robh@kernel.org Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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@ -14,7 +14,6 @@ CONFIG_CPUSETS=y
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_PROFILING=y
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CONFIG_ARCH_VEXPRESS=y
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CONFIG_ARCH_VEXPRESS_DCSCB=y
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CONFIG_ARCH_VEXPRESS_TC2_PM=y
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CONFIG_SMP=y
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CONFIG_HAVE_ARM_ARCH_TIMER=y
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@ -278,15 +278,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
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build a working kernel, you must also enable relevant core
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tile support or Flattened Device Tree based support options.
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config ARCH_VEXPRESS_DCSCB
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bool "Dual Cluster System Control Block (DCSCB) support"
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depends on MCPM
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select ARM_CCI400_PORT_CTRL
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help
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Support for the Dual Cluster System Configuration Block (DCSCB).
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This is needed to provide CPU and cluster power management
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on RTSM implementing big.LITTLE.
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config ARCH_VEXPRESS_SPC
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bool "Versatile Express Serial Power Controller (SPC)"
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select PM_OPP
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@ -16,9 +16,6 @@ obj-$(CONFIG_ARCH_REALVIEW) += realview.o
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# vexpress
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obj-$(CONFIG_ARCH_VEXPRESS) := v2m.o
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obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o
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CFLAGS_dcscb.o += -march=armv7-a
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CFLAGS_REMOVE_dcscb.o = -pg
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obj-$(CONFIG_ARCH_VEXPRESS_SPC) += spc.o
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CFLAGS_REMOVE_spc.o = -pg
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obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o
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@ -1,173 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* dcscb.c - Dual Cluster System Configuration Block
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*
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* Created by: Nicolas Pitre, May 2012
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* Copyright: (C) 2012-2013 Linaro Limited
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/of_address.h>
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#include <linux/vexpress.h>
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#include <linux/arm-cci.h>
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#include <asm/mcpm.h>
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#include <asm/proc-fns.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/cp15.h>
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#include "vexpress.h"
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#define RST_HOLD0 0x0
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#define RST_HOLD1 0x4
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#define SYS_SWRESET 0x8
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#define RST_STAT0 0xc
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#define RST_STAT1 0x10
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#define EAG_CFG_R 0x20
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#define EAG_CFG_W 0x24
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#define KFC_CFG_R 0x28
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#define KFC_CFG_W 0x2c
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#define DCS_CFG_R 0x30
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static void __iomem *dcscb_base;
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static int dcscb_allcpus_mask[2];
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static int dcscb_cpu_powerup(unsigned int cpu, unsigned int cluster)
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{
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unsigned int rst_hold, cpumask = (1 << cpu);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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if (cluster >= 2 || !(cpumask & dcscb_allcpus_mask[cluster]))
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return -EINVAL;
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
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rst_hold &= ~(cpumask | (cpumask << 4));
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
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return 0;
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}
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static int dcscb_cluster_powerup(unsigned int cluster)
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{
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unsigned int rst_hold;
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pr_debug("%s: cluster %u\n", __func__, cluster);
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if (cluster >= 2)
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return -EINVAL;
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/* remove cluster reset and add individual CPU's reset */
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
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rst_hold &= ~(1 << 8);
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rst_hold |= dcscb_allcpus_mask[cluster];
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
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return 0;
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}
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static void dcscb_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
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{
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unsigned int rst_hold;
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= 2 || !((1 << cpu) & dcscb_allcpus_mask[cluster]));
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
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rst_hold |= (1 << cpu);
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
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}
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static void dcscb_cluster_powerdown_prepare(unsigned int cluster)
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{
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unsigned int rst_hold;
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pr_debug("%s: cluster %u\n", __func__, cluster);
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BUG_ON(cluster >= 2);
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
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rst_hold |= (1 << 8);
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
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}
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static void dcscb_cpu_cache_disable(void)
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{
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/* Disable and flush the local CPU cache. */
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v7_exit_coherency_flush(louis);
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}
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static void dcscb_cluster_cache_disable(void)
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{
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/* Flush all cache levels for this cluster. */
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v7_exit_coherency_flush(all);
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/*
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* A full outer cache flush could be needed at this point
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* on platforms with such a cache, depending on where the
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* outer cache sits. In some cases the notion of a "last
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* cluster standing" would need to be implemented if the
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* outer cache is shared across clusters. In any case, when
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* the outer cache needs flushing, there is no concurrent
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* access to the cache controller to worry about and no
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* special locking besides what is already provided by the
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* MCPM state machinery is needed.
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*/
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/*
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* Disable cluster-level coherency by masking
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* incoming snoops and DVM messages:
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*/
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cci_disable_port_by_cpu(read_cpuid_mpidr());
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}
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static const struct mcpm_platform_ops dcscb_power_ops = {
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.cpu_powerup = dcscb_cpu_powerup,
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.cluster_powerup = dcscb_cluster_powerup,
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.cpu_powerdown_prepare = dcscb_cpu_powerdown_prepare,
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.cluster_powerdown_prepare = dcscb_cluster_powerdown_prepare,
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.cpu_cache_disable = dcscb_cpu_cache_disable,
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.cluster_cache_disable = dcscb_cluster_cache_disable,
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};
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extern void dcscb_power_up_setup(unsigned int affinity_level);
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static int __init dcscb_init(void)
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{
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struct device_node *node;
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unsigned int cfg;
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int ret;
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if (!cci_probed())
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return -ENODEV;
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node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb");
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if (!node)
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return -ENODEV;
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dcscb_base = of_iomap(node, 0);
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of_node_put(node);
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if (!dcscb_base)
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return -EADDRNOTAVAIL;
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cfg = readl_relaxed(dcscb_base + DCS_CFG_R);
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dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1;
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dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1;
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ret = mcpm_platform_register(&dcscb_power_ops);
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if (!ret)
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ret = mcpm_sync_init(dcscb_power_up_setup);
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if (ret) {
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iounmap(dcscb_base);
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return ret;
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}
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pr_info("VExpress DCSCB support installed\n");
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/*
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* Future entries into the kernel can now go
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* through the cluster entry vectors.
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*/
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vexpress_flags_set(__pa_symbol(mcpm_entry_point));
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return 0;
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}
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early_initcall(dcscb_init);
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@ -1,33 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Created by: Dave Martin, 2012-06-22
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* Copyright: (C) 2012-2013 Linaro Limited
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*/
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#include <linux/linkage.h>
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ENTRY(dcscb_power_up_setup)
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cmp r0, #0 @ check affinity level
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beq 2f
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/*
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* Enable cluster-level coherency, in preparation for turning on the MMU.
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* The ACTLR SMP bit does not need to be set here, because cpu_resume()
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* already restores that.
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*
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* A15/A7 may not require explicit L2 invalidation on reset, dependent
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* on hardware integration decisions.
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* For now, this code assumes that L2 is either already invalidated,
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* or invalidation is not required.
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*/
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b cci_enable_port_for_self
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2: @ Implementation-specific local CPU setup operations should go here,
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@ if any. In this case, there is nothing to do.
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bx lr
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ENDPROC(dcscb_power_up_setup)
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