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phy: freescale: imx8m-pcie: Refine register definitions

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No function changes, refine PHY register definitions.
- Keep align with other CMN PHY registers, refine the definitions of
  PHY_CMN_REG75.
- Remove two BIT definitions that are not used at all.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Link: https://lore.kernel.org/r/1665625622-20551-3-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Richard Zhu 2022-10-13 09:47:00 +08:00 committed by Vinod Koul
parent 25caed3dca
commit e9e7dca53b
1 changed files with 4 additions and 7 deletions
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11
drivers/phy/freescale/phy-fsl-imx8m-pcie.c
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@ -31,12 +31,10 @@
#define IMX8MM_PCIE_PHY_CMN_REG065 0x194 #define IMX8MM_PCIE_PHY_CMN_REG065 0x194
#define ANA_AUX_RX_TERM (BIT(7) | BIT(4)) #define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
#define ANA_AUX_TX_LVL GENMASK(3, 0) #define ANA_AUX_TX_LVL GENMASK(3, 0)
#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4 #define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3 #define ANA_PLL_DONE 0x3
#define PCIE_PHY_TRSV_REG5 0x414 #define PCIE_PHY_TRSV_REG5 0x414
#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
#define PCIE_PHY_TRSV_REG6 0x418 #define PCIE_PHY_TRSV_REG6 0x418
#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24) #define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3) #define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
@ -131,9 +129,8 @@ static int imx8_pcie_phy_power_on(struct phy *phy)
reset_control_deassert(imx8_phy->reset); reset_control_deassert(imx8_phy->reset);
/* Polling to check the phy is ready or not. */ /* Polling to check the phy is ready or not. */
ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75, ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
val, val == PCIE_PHY_CMN_REG75_PLL_DONE, val, val == ANA_PLL_DONE, 10, 20000);
10, 20000);
return ret; return ret;
} }