watchdog: sa1100: use platform device registration
Rather than relying on machine specific headers to pass down the reboot status and the register locations, use resources and platform_data. Aside from this, keep the changes to a minimum. Cc: Wim Van Sebroeck <wim@linux-watchdog.org> Cc: linux-watchdog@vger.kernel.org Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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@ -24,6 +24,8 @@
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#include <linux/platform_data/mmp_dma.h>
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#include <linux/platform_data/mtd-nand-pxa3xx.h>
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#include <mach/regs-ost.h>
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#include <mach/reset.h>
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#include "devices.h"
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#include "generic.h"
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@ -1118,3 +1120,12 @@ void __init pxa2xx_set_dmac_info(struct mmp_dma_platdata *dma_pdata)
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{
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pxa_register_device(&pxa2xx_pxa_dma, dma_pdata);
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}
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void __init pxa_register_wdt(unsigned int reset_status)
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{
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struct resource res = DEFINE_RES_MEM(OST_PHYS, OST_LEN);
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reset_status &= RESET_STATUS_WATCHDOG;
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platform_device_register_resndata(NULL, "sa1100_wdt", -1, &res, 1,
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&reset_status, sizeof(reset_status));
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}
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@ -7,6 +7,8 @@
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/*
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* OS Timer & Match Registers
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*/
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#define OST_PHYS 0x40A00000
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#define OST_LEN 0x00000020
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#define OSMR0 io_p2v(0x40A00000) /* */
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#define OSMR1 io_p2v(0x40A00004) /* */
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@ -8,8 +8,8 @@
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#define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */
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#define RESET_STATUS_ALL (0xf)
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extern unsigned int reset_status;
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extern void clear_reset_status(unsigned int mask);
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extern void pxa_register_wdt(unsigned int reset_status);
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/**
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* init_gpio_reset() - register GPIO as reset generator
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@ -240,7 +240,7 @@ static int __init pxa25x_init(void)
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if (cpu_is_pxa25x()) {
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reset_status = RCSR;
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pxa_register_wdt(RCSR);
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pxa25x_init_pm();
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@ -337,7 +337,7 @@ static int __init pxa27x_init(void)
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if (cpu_is_pxa27x()) {
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reset_status = RCSR;
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pxa_register_wdt(RCSR);
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pxa27x_init_pm();
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@ -463,7 +463,7 @@ static int __init pxa3xx_init(void)
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if (cpu_is_pxa3xx()) {
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reset_status = ARSR;
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pxa_register_wdt(ARSR);
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/*
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* clear RDH bit every time after reset
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@ -11,9 +11,6 @@
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#include <mach/reset.h>
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#include <mach/smemc.h>
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unsigned int reset_status;
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EXPORT_SYMBOL(reset_status);
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static void do_hw_reset(void);
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static int reset_gpio = -1;
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@ -39,9 +39,6 @@
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#include "generic.h"
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#include <clocksource/pxa.h>
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unsigned int reset_status;
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EXPORT_SYMBOL(reset_status);
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#define NR_FREQS 16
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/*
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@ -319,10 +316,13 @@ static struct platform_device *sa11x0_devices[] __initdata = {
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static int __init sa1100_init(void)
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{
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struct resource wdt_res = DEFINE_RES_MEM(0x90000000, 0x20);
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pm_power_off = sa1100_power_off;
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regulator_has_full_constraints();
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platform_device_register_simple("sa1100_wdt", -1, &wdt_res, 1);
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return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
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}
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@ -10,7 +10,6 @@
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#define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */
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#define RESET_STATUS_ALL (0xf)
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extern unsigned int reset_status;
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static inline void clear_reset_status(unsigned int mask)
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{
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RCSR = mask;
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@ -22,6 +22,7 @@
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/fs.h>
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#include <linux/platform_device.h>
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#include <linux/miscdevice.h>
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#include <linux/watchdog.h>
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#include <linux/init.h>
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@ -30,16 +31,42 @@
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#include <linux/uaccess.h>
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#include <linux/timex.h>
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#ifdef CONFIG_ARCH_PXA
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#include <mach/regs-ost.h>
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#endif
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#define REG_OSMR0 0x0000 /* OS timer Match Reg. 0 */
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#define REG_OSMR1 0x0004 /* OS timer Match Reg. 1 */
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#define REG_OSMR2 0x0008 /* OS timer Match Reg. 2 */
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#define REG_OSMR3 0x000c /* OS timer Match Reg. 3 */
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#define REG_OSCR 0x0010 /* OS timer Counter Reg. */
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#define REG_OSSR 0x0014 /* OS timer Status Reg. */
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#define REG_OWER 0x0018 /* OS timer Watch-dog Enable Reg. */
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#define REG_OIER 0x001C /* OS timer Interrupt Enable Reg. */
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#include <mach/reset.h>
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#define OSSR_M3 (1 << 3) /* Match status channel 3 */
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#define OSSR_M2 (1 << 2) /* Match status channel 2 */
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#define OSSR_M1 (1 << 1) /* Match status channel 1 */
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#define OSSR_M0 (1 << 0) /* Match status channel 0 */
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#define OWER_WME (1 << 0) /* Watchdog Match Enable */
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#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
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#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
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#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
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#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
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static unsigned long oscr_freq;
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static unsigned long sa1100wdt_users;
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static unsigned int pre_margin;
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static int boot_status;
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static void __iomem *reg_base;
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static inline void sa1100_wr(u32 val, u32 offset)
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{
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writel_relaxed(val, reg_base + offset);
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}
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static inline u32 sa1100_rd(u32 offset)
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{
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return readl_relaxed(reg_base + offset);
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}
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/*
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* Allow only one person to hold it open
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@ -50,10 +77,10 @@ static int sa1100dog_open(struct inode *inode, struct file *file)
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return -EBUSY;
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/* Activate SA1100 Watchdog timer */
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writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
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writel_relaxed(OSSR_M3, OSSR);
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writel_relaxed(OWER_WME, OWER);
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writel_relaxed(readl_relaxed(OIER) | OIER_E3, OIER);
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sa1100_wr(sa1100_rd(REG_OSCR) + pre_margin, REG_OSMR3);
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sa1100_wr(OSSR_M3, REG_OSSR);
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sa1100_wr(OWER_WME, REG_OWER);
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sa1100_wr(sa1100_rd(REG_OIER) | OIER_E3, REG_OIER);
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return stream_open(inode, file);
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}
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@ -61,7 +88,7 @@ static int sa1100dog_open(struct inode *inode, struct file *file)
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* The watchdog cannot be disabled.
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*
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* Previous comments suggested that turning off the interrupt by
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* clearing OIER[E3] would prevent the watchdog timing out but this
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* clearing REG_OIER[E3] would prevent the watchdog timing out but this
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* does not appear to be true (at least on the PXA255).
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*/
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static int sa1100dog_release(struct inode *inode, struct file *file)
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@ -76,7 +103,7 @@ static ssize_t sa1100dog_write(struct file *file, const char __user *data,
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{
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if (len)
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/* Refresh OSMR3 timer. */
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writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
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sa1100_wr(sa1100_rd(REG_OSCR) + pre_margin, REG_OSMR3);
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return len;
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}
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@ -110,7 +137,7 @@ static long sa1100dog_ioctl(struct file *file, unsigned int cmd,
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break;
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case WDIOC_KEEPALIVE:
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writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
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sa1100_wr(sa1100_rd(REG_OSCR) + pre_margin, REG_OSMR3);
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ret = 0;
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break;
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@ -125,7 +152,7 @@ static long sa1100dog_ioctl(struct file *file, unsigned int cmd,
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}
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pre_margin = oscr_freq * time;
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writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
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sa1100_wr(sa1100_rd(REG_OSCR) + pre_margin, REG_OSMR3);
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fallthrough;
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case WDIOC_GETTIMEOUT:
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@ -151,12 +178,22 @@ static struct miscdevice sa1100dog_miscdev = {
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.fops = &sa1100dog_fops,
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};
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static int margin __initdata = 60; /* (secs) Default is 1 minute */
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static int margin = 60; /* (secs) Default is 1 minute */
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static struct clk *clk;
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static int __init sa1100dog_init(void)
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static int sa1100dog_probe(struct platform_device *pdev)
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{
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int ret;
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int *platform_data;
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struct resource *res;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENXIO;
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reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
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ret = PTR_ERR_OR_ZERO(reg_base);
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if (ret)
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return ret;
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clk = clk_get(NULL, "OSTIMER0");
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if (IS_ERR(clk)) {
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@ -174,13 +211,9 @@ static int __init sa1100dog_init(void)
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oscr_freq = clk_get_rate(clk);
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/*
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* Read the reset status, and save it for later. If
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* we suspend, RCSR will be cleared, and the watchdog
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* reset reason will be lost.
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*/
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boot_status = (reset_status & RESET_STATUS_WATCHDOG) ?
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WDIOF_CARDRESET : 0;
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platform_data = pdev->dev.platform_data;
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if (platform_data && *platform_data)
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boot_status = WDIOF_CARDRESET;
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pre_margin = oscr_freq * margin;
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ret = misc_register(&sa1100dog_miscdev);
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@ -196,15 +229,21 @@ err:
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return ret;
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}
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static void __exit sa1100dog_exit(void)
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static int sa1100dog_remove(struct platform_device *pdev)
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{
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misc_deregister(&sa1100dog_miscdev);
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clk_disable_unprepare(clk);
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clk_put(clk);
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return 0;
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}
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module_init(sa1100dog_init);
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module_exit(sa1100dog_exit);
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struct platform_driver sa1100dog_driver = {
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.driver.name = "sa1100_wdt",
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.probe = sa1100dog_probe,
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.remove = sa1100dog_remove,
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};
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module_platform_driver(sa1100dog_driver);
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MODULE_AUTHOR("Oleg Drokin <green@crimea.edu>");
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MODULE_DESCRIPTION("SA1100/PXA2xx Watchdog");
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