dmaengine: xilinx: xdma: Ease dma_pool alignment requirements
According to the XDMA datasheet (PG195), the address of any descriptor must be 32 byte aligned. The datasheet also states that a contiguous block of descriptors must not cross a 4k address boundary. Therefore, it is possible to ease the pressure put on the dma_pool allocator just by requiring sufficient alignment and boundary values. Add proper macro definition and change the values passed into the dma_pool_create(). Signed-off-by: Jan Kuliga <jankul@alatek.krakow.pl> Link: https://lore.kernel.org/r/20231218113943.9099-4-jankul@alatek.krakow.pl Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -64,9 +64,10 @@ struct xdma_hw_desc {
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__le64 next_desc;
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__le64 next_desc;
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};
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};
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#define XDMA_DESC_SIZE sizeof(struct xdma_hw_desc)
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#define XDMA_DESC_SIZE sizeof(struct xdma_hw_desc)
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#define XDMA_DESC_BLOCK_SIZE (XDMA_DESC_SIZE * XDMA_DESC_ADJACENT)
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#define XDMA_DESC_BLOCK_SIZE (XDMA_DESC_SIZE * XDMA_DESC_ADJACENT)
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#define XDMA_DESC_BLOCK_ALIGN 4096
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#define XDMA_DESC_BLOCK_ALIGN 32
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#define XDMA_DESC_BLOCK_BOUNDARY 4096
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/*
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/*
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* Channel registers
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* Channel registers
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@ -741,9 +741,8 @@ static int xdma_alloc_chan_resources(struct dma_chan *chan)
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return -EINVAL;
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return -EINVAL;
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}
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}
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xdma_chan->desc_pool = dma_pool_create(dma_chan_name(chan),
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xdma_chan->desc_pool = dma_pool_create(dma_chan_name(chan), dev, XDMA_DESC_BLOCK_SIZE,
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dev, XDMA_DESC_BLOCK_SIZE,
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XDMA_DESC_BLOCK_ALIGN, XDMA_DESC_BLOCK_BOUNDARY);
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XDMA_DESC_BLOCK_ALIGN, 0);
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if (!xdma_chan->desc_pool) {
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if (!xdma_chan->desc_pool) {
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xdma_err(xdev, "unable to allocate descriptor pool");
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xdma_err(xdev, "unable to allocate descriptor pool");
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return -ENOMEM;
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return -ENOMEM;
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