drm/amdgpu : Add mes_log_enable to control mes log feature
The MES log might slow down the performance for extra step of log the data, disable it by default and introduce a parameter can enable it when necessary Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -210,6 +210,7 @@ extern int amdgpu_async_gfx_ring;
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extern int amdgpu_mcbp;
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extern int amdgpu_discovery;
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extern int amdgpu_mes;
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extern int amdgpu_mes_log_enable;
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extern int amdgpu_mes_kiq;
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extern int amdgpu_noretry;
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extern int amdgpu_force_asic_type;
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@ -195,6 +195,7 @@ int amdgpu_async_gfx_ring = 1;
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int amdgpu_mcbp = -1;
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int amdgpu_discovery = -1;
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int amdgpu_mes;
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int amdgpu_mes_log_enable = 0;
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int amdgpu_mes_kiq;
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int amdgpu_noretry = -1;
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int amdgpu_force_asic_type = -1;
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@ -667,6 +668,15 @@ MODULE_PARM_DESC(mes,
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"Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
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module_param_named(mes, amdgpu_mes, int, 0444);
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/**
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* DOC: mes_log_enable (int)
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* Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log.
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* (0 = disabled (default), 1 = enabled)
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*/
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MODULE_PARM_DESC(mes_log_enable,
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"Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)");
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module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444);
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/**
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* DOC: mes_kiq (int)
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* Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
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@ -100,6 +100,9 @@ static int amdgpu_mes_event_log_init(struct amdgpu_device *adev)
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{
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int r;
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if (!amdgpu_mes_log_enable)
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return 0;
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r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_GTT,
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&adev->mes.event_log_gpu_obj,
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@ -1561,7 +1564,7 @@ void amdgpu_debugfs_mes_event_log_init(struct amdgpu_device *adev)
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#if defined(CONFIG_DEBUG_FS)
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struct drm_minor *minor = adev_to_drm(adev)->primary;
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struct dentry *root = minor->debugfs_root;
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if (adev->enable_mes)
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if (adev->enable_mes && amdgpu_mes_log_enable)
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debugfs_create_file("amdgpu_mes_event_log", 0444, root,
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adev, &amdgpu_debugfs_mes_event_log_fops);
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@ -411,8 +411,11 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
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mes_set_hw_res_pkt.enable_reg_active_poll = 1;
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mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
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mes_set_hw_res_pkt.oversubscription_timer = 50;
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mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
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mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr;
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if (amdgpu_mes_log_enable) {
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mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
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mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr =
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mes->event_log_gpu_addr;
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}
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return mes_v11_0_submit_pkt_and_poll_completion(mes,
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&mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
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