x86/resctrl: Pass domain to target CPU
reset_all_ctrls() and resctrl_arch_update_domains() use on_each_cpu_mask()
to call rdt_ctrl_update() on potentially one CPU from each domain.
But this means rdt_ctrl_update() needs to figure out which domain to
apply changes to. Doing so requires a search of all domains in a resource,
which can only be done safely if cpus_lock is held. Both callers do hold
this lock, but there isn't a way for a function called on another CPU
via IPI to verify this.
Commit
c0d848fcb0
("x86/resctrl: Remove lockdep annotation that triggers
false positive")
removed the incorrect assertions.
Add the target domain to the msr_param structure and call
rdt_ctrl_update() for each domain separately using
smp_call_function_single(). This means that rdt_ctrl_update() doesn't
need to search for the domain and get_domain_from_cpu() can safely
assert that the cpus_lock is held since the remaining callers do not use
IPI.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Reviewed-by: James Morse <james.morse@arm.com>
Reviewed-by: Babu Moger <babu.moger@amd.com>
Tested-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Link: https://lore.kernel.org/r/20240308213846.77075-2-tony.luck@intel.com
This commit is contained in:
parent
ed30a4a51b
commit
e3ca96e479
@ -362,6 +362,8 @@ struct rdt_domain *get_domain_from_cpu(int cpu, struct rdt_resource *r)
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{
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struct rdt_domain *d;
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lockdep_assert_cpus_held();
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list_for_each_entry(d, &r->domains, list) {
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/* Find the domain that contains this CPU */
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if (cpumask_test_cpu(cpu, &d->cpu_mask))
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@ -378,19 +380,11 @@ u32 resctrl_arch_get_num_closid(struct rdt_resource *r)
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void rdt_ctrl_update(void *arg)
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{
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struct rdt_hw_resource *hw_res;
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struct msr_param *m = arg;
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struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res);
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struct rdt_resource *r = m->res;
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int cpu = smp_processor_id();
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struct rdt_domain *d;
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d = get_domain_from_cpu(cpu, r);
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if (d) {
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hw_res->msr_update(d, m, r);
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return;
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}
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pr_warn_once("cpu %d not found in any domain for resource %s\n",
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cpu, r->name);
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hw_res = resctrl_to_arch_res(m->res);
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hw_res->msr_update(m->dom, m, m->res);
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}
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/*
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@ -463,6 +457,7 @@ static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d)
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hw_dom->ctrl_val = dc;
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setup_default_ctrlval(r, dc);
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m.dom = d;
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m.low = 0;
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m.high = hw_res->num_closid;
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hw_res->msr_update(d, &m, r);
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@ -272,22 +272,6 @@ static u32 get_config_index(u32 closid, enum resctrl_conf_type type)
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}
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}
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static bool apply_config(struct rdt_hw_domain *hw_dom,
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struct resctrl_staged_config *cfg, u32 idx,
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cpumask_var_t cpu_mask)
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{
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struct rdt_domain *dom = &hw_dom->d_resctrl;
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if (cfg->new_ctrl != hw_dom->ctrl_val[idx]) {
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cpumask_set_cpu(cpumask_any(&dom->cpu_mask), cpu_mask);
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hw_dom->ctrl_val[idx] = cfg->new_ctrl;
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return true;
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}
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return false;
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}
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int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_domain *d,
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u32 closid, enum resctrl_conf_type t, u32 cfg_val)
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{
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@ -302,6 +286,7 @@ int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_domain *d,
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hw_dom->ctrl_val[idx] = cfg_val;
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msr_param.res = r;
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msr_param.dom = d;
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msr_param.low = idx;
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msr_param.high = idx + 1;
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hw_res->msr_update(d, &msr_param, r);
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@ -315,48 +300,39 @@ int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid)
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struct rdt_hw_domain *hw_dom;
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struct msr_param msr_param;
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enum resctrl_conf_type t;
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cpumask_var_t cpu_mask;
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struct rdt_domain *d;
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u32 idx;
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/* Walking r->domains, ensure it can't race with cpuhp */
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lockdep_assert_cpus_held();
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if (!zalloc_cpumask_var(&cpu_mask, GFP_KERNEL))
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return -ENOMEM;
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msr_param.res = NULL;
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list_for_each_entry(d, &r->domains, list) {
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hw_dom = resctrl_to_arch_dom(d);
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msr_param.res = NULL;
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for (t = 0; t < CDP_NUM_TYPES; t++) {
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cfg = &hw_dom->d_resctrl.staged_config[t];
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if (!cfg->have_new_ctrl)
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continue;
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idx = get_config_index(closid, t);
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if (!apply_config(hw_dom, cfg, idx, cpu_mask))
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if (cfg->new_ctrl == hw_dom->ctrl_val[idx])
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continue;
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hw_dom->ctrl_val[idx] = cfg->new_ctrl;
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if (!msr_param.res) {
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msr_param.low = idx;
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msr_param.high = msr_param.low + 1;
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msr_param.res = r;
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msr_param.dom = d;
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} else {
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msr_param.low = min(msr_param.low, idx);
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msr_param.high = max(msr_param.high, idx + 1);
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}
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}
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if (msr_param.res)
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smp_call_function_any(&d->cpu_mask, rdt_ctrl_update, &msr_param, 1);
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}
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if (cpumask_empty(cpu_mask))
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goto done;
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/* Update resource control msr on all the CPUs. */
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on_each_cpu_mask(cpu_mask, rdt_ctrl_update, &msr_param, 1);
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done:
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free_cpumask_var(cpu_mask);
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return 0;
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}
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@ -379,11 +379,13 @@ static inline struct rdt_hw_domain *resctrl_to_arch_dom(struct rdt_domain *r)
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/**
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* struct msr_param - set a range of MSRs from a domain
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* @res: The resource to use
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* @dom: The domain to update
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* @low: Beginning index from base MSR
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* @high: End index
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*/
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struct msr_param {
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struct rdt_resource *res;
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struct rdt_domain *dom;
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u32 low;
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u32 high;
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};
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@ -2813,16 +2813,12 @@ static int reset_all_ctrls(struct rdt_resource *r)
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struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
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struct rdt_hw_domain *hw_dom;
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struct msr_param msr_param;
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cpumask_var_t cpu_mask;
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struct rdt_domain *d;
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int i;
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/* Walking r->domains, ensure it can't race with cpuhp */
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lockdep_assert_cpus_held();
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if (!zalloc_cpumask_var(&cpu_mask, GFP_KERNEL))
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return -ENOMEM;
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msr_param.res = r;
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msr_param.low = 0;
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msr_param.high = hw_res->num_closid;
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@ -2834,17 +2830,13 @@ static int reset_all_ctrls(struct rdt_resource *r)
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*/
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list_for_each_entry(d, &r->domains, list) {
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hw_dom = resctrl_to_arch_dom(d);
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cpumask_set_cpu(cpumask_any(&d->cpu_mask), cpu_mask);
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for (i = 0; i < hw_res->num_closid; i++)
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hw_dom->ctrl_val[i] = r->default_ctrl;
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msr_param.dom = d;
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smp_call_function_any(&d->cpu_mask, rdt_ctrl_update, &msr_param, 1);
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}
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/* Update CBM on all the CPUs in cpu_mask */
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on_each_cpu_mask(cpu_mask, rdt_ctrl_update, &msr_param, 1);
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free_cpumask_var(cpu_mask);
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return 0;
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}
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