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usb: cdns2: Fix controller reset issue

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Patch fixes the procedure of resetting controller.
The CPUCTRL register is write only and reading returns 0.
Waiting for reset to complite is incorrect.

Fixes: 3eb1f1efe2 ("usb: cdns2: Add main part of Cadence USBHS driver")
cc: stable@vger.kernel.org
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Link: https://lore.kernel.org/r/PH7PR07MB9538D56D75F1F399D0BB96F0DD922@PH7PR07MB9538.namprd07.prod.outlook.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Pawel Laszczak 2024-09-02 11:09:16 +00:00 committed by Greg Kroah-Hartman
parent 9149c9b0c7
commit e294092811
2 changed files with 12 additions and 9 deletions
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12
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
View File

@ -2251,7 +2251,6 @@ static int cdns2_gadget_start(struct cdns2_device *pdev)
{
u32 max_speed;
void *buf;
int val;
int ret;
pdev->usb_regs = pdev->regs;
@ -2261,14 +2260,9 @@ static int cdns2_gadget_start(struct cdns2_device *pdev)
pdev->adma_regs = pdev->regs + CDNS2_ADMA_REGS_OFFSET;
/* Reset controller. */
set_reg_bit_8(&pdev->usb_regs->cpuctrl, CPUCTRL_SW_RST);
ret = readl_poll_timeout_atomic(&pdev->usb_regs->cpuctrl, val,
!(val & CPUCTRL_SW_RST), 1, 10000);
if (ret) {
dev_err(pdev->dev, "Error: reset controller timeout\n");
return -EINVAL;
}
writeb(CPUCTRL_SW_RST | CPUCTRL_UPCLK | CPUCTRL_WUEN,
&pdev->usb_regs->cpuctrl);
usleep_range(5, 10);
usb_initialize_gadget(pdev->dev, &pdev->gadget, NULL);

9
drivers/usb/gadget/udc/cdns2/cdns2-gadget.h
View File

@ -292,8 +292,17 @@ struct cdns2_usb_regs {
#define SPEEDCTRL_HSDISABLE BIT(7)
/* CPUCTRL- bitmasks. */
/* UP clock enable */
#define CPUCTRL_UPCLK BIT(0)
/* Controller reset bit. */
#define CPUCTRL_SW_RST BIT(1)
/**
* If the wuen bit is ‘1’, the upclken is automatically set to ‘1’ after
* detecting rising edge of wuintereq interrupt. If the wuen bit is ‘0’,
* the wuintereq interrupt is ignored.
*/
#define CPUCTRL_WUEN BIT(7)
/**
* struct cdns2_adma_regs - ADMA controller registers.