drm/amdgpu: Add enforce_isolation sysfs attribute
This commit adds a new sysfs attribute 'enforce_isolation' to control the 'enforce_isolation' setting per GPU. The attribute can be read and written, and accepts values 0 (disabled) and 1 (enabled). When 'enforce_isolation' is enabled, reserved VMIDs are allocated for each ring. When it's disabled, the reserved VMIDs are freed. The set function locks a mutex before changing the 'enforce_isolation' flag and the VMIDs, and unlocks it afterwards. This ensures that these operations are atomic and prevents race conditions and other concurrency issues. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1164,6 +1164,8 @@ struct amdgpu_device {
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bool debug_enable_ras_aca;
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bool enforce_isolation[MAX_XCP];
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/* Added this mutex for cleaner shader isolation between GFX and compute processes */
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struct mutex enforce_isolation_mutex;
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};
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static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
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@ -4065,6 +4065,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
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mutex_init(&adev->pm.stable_pstate_ctx_lock);
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mutex_init(&adev->benchmark_mutex);
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mutex_init(&adev->gfx.reset_sem_mutex);
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/* Initialize the mutex for cleaner shader isolation between GFX and compute processes */
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mutex_init(&adev->enforce_isolation_mutex);
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amdgpu_device_init_apu_flags(adev);
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@ -1391,6 +1391,88 @@ static ssize_t amdgpu_gfx_get_available_compute_partition(struct device *dev,
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return sysfs_emit(buf, "%s\n", supported_partition);
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}
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static ssize_t amdgpu_gfx_get_enforce_isolation(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = drm_to_adev(ddev);
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int i;
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ssize_t size = 0;
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if (adev->xcp_mgr) {
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for (i = 0; i < adev->xcp_mgr->num_xcps; i++) {
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size += sysfs_emit_at(buf, size, "%u", adev->enforce_isolation[i]);
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if (i < (adev->xcp_mgr->num_xcps - 1))
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size += sysfs_emit_at(buf, size, " ");
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}
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buf[size++] = '\n';
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} else {
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size = sysfs_emit_at(buf, 0, "%u\n", adev->enforce_isolation[0]);
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}
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return size;
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}
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static ssize_t amdgpu_gfx_set_enforce_isolation(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = drm_to_adev(ddev);
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long partition_values[MAX_XCP] = {0};
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int ret, i, num_partitions;
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const char *input_buf = buf;
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for (i = 0; i < (adev->xcp_mgr ? adev->xcp_mgr->num_xcps : 1); i++) {
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ret = sscanf(input_buf, "%ld", &partition_values[i]);
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if (ret <= 0)
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break;
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/* Move the pointer to the next value in the string */
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input_buf = strchr(input_buf, ' ');
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if (input_buf) {
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input_buf++;
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} else {
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i++;
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break;
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}
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}
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num_partitions = i;
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if (adev->xcp_mgr && num_partitions != adev->xcp_mgr->num_xcps)
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return -EINVAL;
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if (!adev->xcp_mgr && num_partitions != 1)
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return -EINVAL;
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for (i = 0; i < num_partitions; i++) {
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if (partition_values[i] != 0 && partition_values[i] != 1)
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return -EINVAL;
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}
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mutex_lock(&adev->enforce_isolation_mutex);
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for (i = 0; i < num_partitions; i++) {
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if (adev->enforce_isolation[i] && !partition_values[i]) {
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/* Going from enabled to disabled */
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amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(i));
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} else if (!adev->enforce_isolation[i] && partition_values[i]) {
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/* Going from disabled to enabled */
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amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(i));
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}
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adev->enforce_isolation[i] = partition_values[i];
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}
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mutex_unlock(&adev->enforce_isolation_mutex);
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return count;
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}
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static DEVICE_ATTR(enforce_isolation, 0644,
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amdgpu_gfx_get_enforce_isolation,
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amdgpu_gfx_set_enforce_isolation);
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static DEVICE_ATTR(current_compute_partition, 0644,
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amdgpu_gfx_get_current_compute_partition,
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amdgpu_gfx_set_compute_partition);
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@ -1417,6 +1499,25 @@ void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev)
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device_remove_file(adev->dev, &dev_attr_available_compute_partition);
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}
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int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev)
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{
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int r;
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if (!amdgpu_sriov_vf(adev)) {
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r = device_create_file(adev->dev, &dev_attr_enforce_isolation);
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if (r)
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return r;
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}
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return 0;
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}
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void amdgpu_gfx_sysfs_isolation_shader_fini(struct amdgpu_device *adev)
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{
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if (!amdgpu_sriov_vf(adev))
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device_remove_file(adev->dev, &dev_attr_enforce_isolation);
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}
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int amdgpu_gfx_cleaner_shader_sw_init(struct amdgpu_device *adev,
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unsigned int cleaner_shader_size)
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{
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@ -561,6 +561,8 @@ void amdgpu_gfx_cleaner_shader_sw_fini(struct amdgpu_device *adev);
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void amdgpu_gfx_cleaner_shader_init(struct amdgpu_device *adev,
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unsigned int cleaner_shader_size,
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const void *cleaner_shader_ptr);
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int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev);
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void amdgpu_gfx_sysfs_isolation_shader_fini(struct amdgpu_device *adev);
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static inline const char *amdgpu_gfx_compute_mode_desc(int mode)
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{
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