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Xtensa updates for v6.6

- enable MTD XIP support
 - fix base address of the xtensa perf module in newer hardware
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Merge tag 'xtensa-20230905' of https://github.com/jcmvbkbc/linux-xtensa

Pull xtensa updates from Max Filippov:

 - enable MTD XIP support

 - fix base address of the xtensa perf module in newer hardware

* tag 'xtensa-20230905' of https://github.com/jcmvbkbc/linux-xtensa:
  xtensa: add XIP-aware MTD support
  xtensa: PMU: fix base address for the newer hardware
This commit is contained in:
Linus Torvalds 2023-09-07 10:30:17 -07:00
commit dd1386dd3c
7 changed files with 56 additions and 5 deletions

View File

@ -71,6 +71,9 @@ config ARCH_HAS_ILOG2_U32
config ARCH_HAS_ILOG2_U64
def_bool n
config ARCH_MTD_XIP
def_bool y
config NO_IOPORT_MAP
def_bool n

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@ -52,4 +52,13 @@
#define XTENSA_STACK_ALIGNMENT 16
#endif
#ifndef XCHAL_HW_MIN_VERSION
#if defined(XCHAL_HW_MIN_VERSION_MAJOR) && defined(XCHAL_HW_MIN_VERSION_MINOR)
#define XCHAL_HW_MIN_VERSION (XCHAL_HW_MIN_VERSION_MAJOR * 100 + \
XCHAL_HW_MIN_VERSION_MINOR)
#else
#define XCHAL_HW_MIN_VERSION 0
#endif
#endif
#endif

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@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _ASM_MTD_XIP_H
#define _ASM_MTD_XIP_H
#include <asm/processor.h>
#define xip_irqpending() (xtensa_get_sr(interrupt) & xtensa_get_sr(intenable))
#define xip_currtime() (xtensa_get_sr(ccount))
#define xip_elapsed_since(x) ((xtensa_get_sr(ccount) - (x)) / 1000) /* should work up to 1GHz */
#define xip_cpu_idle() do { asm volatile ("waiti 0"); } while (0)
#endif /* _ASM_MTD_XIP_H */

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@ -34,6 +34,10 @@ extern char _SecondaryResetVector_text_start[];
extern char _SecondaryResetVector_text_end[];
#endif
#ifdef CONFIG_XIP_KERNEL
#ifdef CONFIG_VECTORS_ADDR
extern char _xip_text_start[];
extern char _xip_text_end[];
#endif
extern char _xip_start[];
extern char _xip_end[];
#endif

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@ -13,17 +13,26 @@
#include <linux/perf_event.h>
#include <linux/platform_device.h>
#include <asm/core.h>
#include <asm/processor.h>
#include <asm/stacktrace.h>
#define XTENSA_HWVERSION_RG_2015_0 260000
#if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RG_2015_0
#define XTENSA_PMU_ERI_BASE 0x00101000
#else
#define XTENSA_PMU_ERI_BASE 0x00001000
#endif
/* Global control/status for all perf counters */
#define XTENSA_PMU_PMG 0x1000
#define XTENSA_PMU_PMG XTENSA_PMU_ERI_BASE
/* Perf counter values */
#define XTENSA_PMU_PM(i) (0x1080 + (i) * 4)
#define XTENSA_PMU_PM(i) (XTENSA_PMU_ERI_BASE + 0x80 + (i) * 4)
/* Perf counter control registers */
#define XTENSA_PMU_PMCTRL(i) (0x1100 + (i) * 4)
#define XTENSA_PMU_PMCTRL(i) (XTENSA_PMU_ERI_BASE + 0x100 + (i) * 4)
/* Perf counter status registers */
#define XTENSA_PMU_PMSTAT(i) (0x1180 + (i) * 4)
#define XTENSA_PMU_PMSTAT(i) (XTENSA_PMU_ERI_BASE + 0x180 + (i) * 4)
#define XTENSA_PMU_PMG_PMEN 0x1

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@ -311,6 +311,9 @@ void __init setup_arch(char **cmdline_p)
mem_reserve(__pa(_stext), __pa(_end));
#ifdef CONFIG_XIP_KERNEL
#ifdef CONFIG_VECTORS_ADDR
mem_reserve(__pa(_xip_text_start), __pa(_xip_text_end));
#endif
mem_reserve(__pa(_xip_start), __pa(_xip_end));
#endif

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@ -118,6 +118,7 @@ SECTIONS
SECTION_VECTOR2 (.DoubleExceptionVector.text, DOUBLEEXC_VECTOR_VADDR)
*(.exception.text)
*(.xiptext)
#endif
IRQENTRY_TEXT
@ -201,6 +202,9 @@ SECTIONS
.DebugInterruptVector.text);
RELOCATE_ENTRY(_exception_text,
.exception.text);
#ifdef CONFIG_XIP_KERNEL
RELOCATE_ENTRY(_xip_text, .xiptext);
#endif
#endif
#ifdef CONFIG_XIP_KERNEL
RELOCATE_ENTRY(_xip_data, .data);
@ -319,7 +323,12 @@ SECTIONS
LAST)
#undef LAST
#define LAST .exception.text
SECTION_VECTOR4 (_xip_text,
.xiptext,
,
LAST)
#undef LAST
#define LAST .xiptext
#endif
. = (LOADADDR(LAST) + SIZEOF(LAST) + 3) & ~ 3;