wifi: rtw89: 8852c: Fix TSSI causes transmit power inaccuracy
Modify TSSI ADC FIFO Clock follow RX ADC Clock can avoid transmit power inaccuracy. Signed-off-by: Kuan-Chung Chen <damon.chen@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20230830092849.153251-3-pkshih@realtek.com
This commit is contained in:
Kuan-Chung Chen
Kalle Valo
parent
8f969ba1de
commit
dae4464939
@ -4539,6 +4539,8 @@
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#define B_P0_TSSI_ALIM2 GENMASK(29, 0)
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#define R_P0_TSSI_ALIM4 0x5640
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#define R_TSSI_PA_K8 0x5644
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#define R_P0_TSSI_ADC_CLK 0x566c
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#define B_P0_TSSI_ADC_CLK GENMASK(17, 16)
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#define R_UPD_CLK 0x5670
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#define B_DAC_VAL BIT(31)
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#define B_ACK_VAL GENMASK(30, 29)
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@ -4651,6 +4653,8 @@
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#define B_P1_TSSI_ALIM31 GENMASK(9, 0)
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#define R_P1_TSSI_ALIM2 0x763c
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#define B_P1_TSSI_ALIM2 GENMASK(29, 0)
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#define R_P1_TSSI_ADC_CLK 0x766c
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#define B_P1_TSSI_ADC_CLK GENMASK(17, 16)
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#define R_P1_TSSIC 0x7814
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#define B_P1_TSSIC_BYPASS BIT(11)
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#define R_P1_TMETER 0x7810
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@ -2893,18 +2893,37 @@ static void _tssi_set_sys(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
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enum rtw89_rf_path path)
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{
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const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
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enum rtw89_bandwidth bw = chan->band_width;
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enum rtw89_band band = chan->band_type;
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u32 clk = 0x0;
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rtw89_rfk_parser(rtwdev, &rtw8852c_tssi_sys_defs_tbl);
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if (path == RF_PATH_A)
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switch (bw) {
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case RTW89_CHANNEL_WIDTH_80:
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clk = 0x1;
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break;
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case RTW89_CHANNEL_WIDTH_80_80:
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case RTW89_CHANNEL_WIDTH_160:
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clk = 0x2;
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break;
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default:
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break;
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}
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if (path == RF_PATH_A) {
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rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ADC_CLK,
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B_P0_TSSI_ADC_CLK, clk);
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rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
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&rtw8852c_tssi_sys_defs_2g_a_tbl,
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&rtw8852c_tssi_sys_defs_5g_a_tbl);
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else
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} else {
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rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_ADC_CLK,
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B_P1_TSSI_ADC_CLK, clk);
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rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
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&rtw8852c_tssi_sys_defs_2g_b_tbl,
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&rtw8852c_tssi_sys_defs_5g_b_tbl);
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}
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}
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static void _tssi_ini_txpwr_ctrl_bb(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
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@ -165,11 +165,11 @@ static const struct rtw89_reg5_def rtw8852c_tssi_sys_defs[] = {
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RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0xb5b5),
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RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0xb5b5),
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RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16),
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RTW89_DECL_RFK_WM(0x0304, 0x0000ffff, 0x1f19),
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RTW89_DECL_RFK_WM(0x0308, 0xff000000, 0x1c),
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RTW89_DECL_RFK_WM(0x0304, 0x0000ffff, 0x1313),
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RTW89_DECL_RFK_WM(0x0308, 0xff000000, 0x13),
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RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041),
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RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041),
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RTW89_DECL_RFK_WM(0x0324, 0xffff0000, 0x2001),
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RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x00410041),
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RTW89_DECL_RFK_WM(0x0324, 0xffff0000, 0x0041),
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RTW89_DECL_RFK_WM(0x0020, 0x00006000, 0x3),
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RTW89_DECL_RFK_WM(0x0024, 0x00006000, 0x3),
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RTW89_DECL_RFK_WM(0x0704, 0xffff0000, 0x601e),
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@ -222,7 +222,7 @@ static const struct rtw89_reg5_def rtw8852c_tssi_txpwr_ctrl_bb_defs_a[] = {
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RTW89_DECL_RFK_WM(0x5810, 0xffffffff, 0x59010000),
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RTW89_DECL_RFK_WM(0x5814, 0x01ffffff, 0x026d000),
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RTW89_DECL_RFK_WM(0x5814, 0xf8000000, 0x00),
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RTW89_DECL_RFK_WM(0x5818, 0xffffffff, 0x002c1800),
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RTW89_DECL_RFK_WM(0x5818, 0xffffffff, 0x002c18e8),
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RTW89_DECL_RFK_WM(0x581c, 0x3fffffff, 0x3dc80280),
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RTW89_DECL_RFK_WM(0x5820, 0xffffffff, 0x00000080),
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RTW89_DECL_RFK_WM(0x58e8, 0x0000003f, 0x03),
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@ -251,7 +251,7 @@ static const struct rtw89_reg5_def rtw8852c_tssi_txpwr_ctrl_bb_defs_a[] = {
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RTW89_DECL_RFK_WM(0x58d4, 0x07fc0000, 0x100),
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RTW89_DECL_RFK_WM(0x58d8, 0xffffffff, 0x8008016c),
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RTW89_DECL_RFK_WM(0x58dc, 0x0001ffff, 0x0807f),
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RTW89_DECL_RFK_WM(0x58dc, 0xfff00000, 0x800),
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RTW89_DECL_RFK_WM(0x58dc, 0xfff00000, 0xc00),
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RTW89_DECL_RFK_WM(0x58f0, 0x0003ffff, 0x001ff),
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RTW89_DECL_RFK_WM(0x58f4, 0x000fffff, 0x000),
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RTW89_DECL_RFK_WM(0x58f8, 0x000fffff, 0x000),
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@ -260,14 +260,14 @@ static const struct rtw89_reg5_def rtw8852c_tssi_txpwr_ctrl_bb_defs_a[] = {
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RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_txpwr_ctrl_bb_defs_a);
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static const struct rtw89_reg5_def rtw8852c_tssi_txpwr_ctrl_bb_defs_b[] = {
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RTW89_DECL_RFK_WM(0x566c, 0x00001000, 0x0),
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RTW89_DECL_RFK_WM(0x766c, 0x00001000, 0x0),
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RTW89_DECL_RFK_WM(0x7800, 0xffffffff, 0x003f807f),
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RTW89_DECL_RFK_WM(0x780c, 0x0000007f, 0x40),
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RTW89_DECL_RFK_WM(0x780c, 0x0fffff00, 0x00040),
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RTW89_DECL_RFK_WM(0x7810, 0xffffffff, 0x59010000),
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RTW89_DECL_RFK_WM(0x7814, 0x01ffffff, 0x026d000),
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RTW89_DECL_RFK_WM(0x7814, 0xf8000000, 0x00),
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RTW89_DECL_RFK_WM(0x7818, 0xffffffff, 0x002c1800),
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RTW89_DECL_RFK_WM(0x7818, 0xffffffff, 0x002c18e8),
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RTW89_DECL_RFK_WM(0x781c, 0x3fffffff, 0x3dc80280),
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RTW89_DECL_RFK_WM(0x7820, 0xffffffff, 0x00000080),
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RTW89_DECL_RFK_WM(0x78e8, 0x0000003f, 0x03),
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@ -296,7 +296,7 @@ static const struct rtw89_reg5_def rtw8852c_tssi_txpwr_ctrl_bb_defs_b[] = {
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RTW89_DECL_RFK_WM(0x78d4, 0x07fc0000, 0x100),
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RTW89_DECL_RFK_WM(0x78d8, 0xffffffff, 0x8008016c),
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RTW89_DECL_RFK_WM(0x78dc, 0x0001ffff, 0x0807f),
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RTW89_DECL_RFK_WM(0x78dc, 0xfff00000, 0x800),
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RTW89_DECL_RFK_WM(0x78dc, 0xfff00000, 0xc00),
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RTW89_DECL_RFK_WM(0x78f0, 0x0003ffff, 0x001ff),
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RTW89_DECL_RFK_WM(0x78f4, 0x000fffff, 0x000),
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RTW89_DECL_RFK_WM(0x78f8, 0x000fffff, 0x000),
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@ -511,9 +511,9 @@ static const struct rtw89_reg5_def rtw8852c_tssi_set_aligk_default_defs_5g_a[] =
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RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
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RTW89_DECL_RFK_WM(0x5640, 0x000003ff, 0x000),
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RTW89_DECL_RFK_WM(0x5640, 0x000ffc00, 0x000),
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RTW89_DECL_RFK_WM(0x5640, 0x3ff00000, 0x000),
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RTW89_DECL_RFK_WM(0x5644, 0x000003ff, 0x000),
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RTW89_DECL_RFK_WM(0x5644, 0x000ffc00, 0x000),
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RTW89_DECL_RFK_WM(0x5640, 0x3ff00000, 0x3e9),
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RTW89_DECL_RFK_WM(0x5644, 0x000003ff, 0x039),
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RTW89_DECL_RFK_WM(0x5644, 0x000ffc00, 0x07d),
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};
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RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_set_aligk_default_defs_5g_a);
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@ -531,9 +531,9 @@ static const struct rtw89_reg5_def rtw8852c_tssi_set_aligk_default_defs_5g_b[] =
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RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
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RTW89_DECL_RFK_WM(0x7640, 0x000003ff, 0x000),
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RTW89_DECL_RFK_WM(0x7640, 0x000ffc00, 0x000),
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RTW89_DECL_RFK_WM(0x7640, 0x3ff00000, 0x000),
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RTW89_DECL_RFK_WM(0x7644, 0x000003ff, 0x000),
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RTW89_DECL_RFK_WM(0x7644, 0x000ffc00, 0x000),
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RTW89_DECL_RFK_WM(0x7640, 0x3ff00000, 0x3e9),
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RTW89_DECL_RFK_WM(0x7644, 0x000003ff, 0x039),
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RTW89_DECL_RFK_WM(0x7644, 0x000ffc00, 0x07d),
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};
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RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_set_aligk_default_defs_5g_b);
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@ -551,9 +551,9 @@ static const struct rtw89_reg5_def rtw8852c_tssi_set_aligk_default_defs_6g_a[] =
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RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
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RTW89_DECL_RFK_WM(0x5640, 0x000003ff, 0x000),
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RTW89_DECL_RFK_WM(0x5640, 0x000ffc00, 0x000),
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RTW89_DECL_RFK_WM(0x5640, 0x3ff00000, 0x000),
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RTW89_DECL_RFK_WM(0x5644, 0x000003ff, 0x000),
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RTW89_DECL_RFK_WM(0x5644, 0x000ffc00, 0x000),
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RTW89_DECL_RFK_WM(0x5640, 0x3ff00000, 0x3e9),
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RTW89_DECL_RFK_WM(0x5644, 0x000003ff, 0x039),
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RTW89_DECL_RFK_WM(0x5644, 0x000ffc00, 0x080),
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};
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RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_set_aligk_default_defs_6g_a);
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@ -571,9 +571,9 @@ static const struct rtw89_reg5_def rtw8852c_tssi_set_aligk_default_defs_6g_b[] =
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RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
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RTW89_DECL_RFK_WM(0x7640, 0x000003ff, 0x000),
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RTW89_DECL_RFK_WM(0x7640, 0x000ffc00, 0x000),
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RTW89_DECL_RFK_WM(0x7640, 0x3ff00000, 0x000),
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RTW89_DECL_RFK_WM(0x7644, 0x000003ff, 0x000),
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RTW89_DECL_RFK_WM(0x7644, 0x000ffc00, 0x000),
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RTW89_DECL_RFK_WM(0x7640, 0x3ff00000, 0x3e9),
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RTW89_DECL_RFK_WM(0x7644, 0x000003ff, 0x039),
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RTW89_DECL_RFK_WM(0x7644, 0x000ffc00, 0x080),
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};
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RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_set_aligk_default_defs_6g_b);
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