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pinctrl: mediatek: common: add mt8365_set_clr_mode() callback for broken SET/CLR modes

On MT8365, the SET/CLR of the mode is broken and some pin modes won't
be set correctly.
Add mt8365_set_clr_mode() callback for such SoCs, so that instead of
using the SET/CLR register, use the main R/W register to
read/update/write the modes.

Co-developed-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Link: https://lore.kernel.org/r/20221021084708.1109986-2-bchihi@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Balsam CHIHI 2022-10-21 10:47:07 +02:00 committed by Linus Walleij
parent 76f3768132
commit d459a23522
2 changed files with 22 additions and 1 deletions

View File

@ -330,6 +330,21 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
return -EINVAL;
}
if (pctl->devdata->mt8365_set_clr_mode) {
bit = pin & pctl->devdata->mode_mask;
reg_pullen = mtk_get_port(pctl, pin) +
pctl->devdata->pullen_offset;
reg_pullsel = mtk_get_port(pctl, pin) +
pctl->devdata->pullsel_offset;
ret = pctl->devdata->mt8365_set_clr_mode(mtk_get_regmap(pctl, pin),
bit, reg_pullen, reg_pullsel,
enable, isup);
if (ret)
return -EINVAL;
return 0;
}
bit = BIT(pin & pctl->devdata->mode_mask);
if (enable)
reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +

View File

@ -216,7 +216,10 @@ struct mtk_eint_offsets {
* @spec_dir_set: In very few SoCs, direction control registers are not
* arranged continuously, they may be cut to parts. So they need special
* dir setting.
* @mt8365_set_clr_mode: In mt8365, some pins won't set correcty because they
* need to use the main R/W register to read/update/write the modes instead of
* the SET/CLR register.
*
* @dir_offset: The direction register offset.
* @pullen_offset: The pull-up/pull-down enable register offset.
* @pinmux_offset: The pinmux register offset.
@ -252,6 +255,9 @@ struct mtk_pinctrl_devdata {
void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
unsigned int mode);
void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
int (*mt8365_set_clr_mode)(struct regmap *regmap,
unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel,
bool enable, bool isup);
unsigned int dir_offset;
unsigned int ies_offset;
unsigned int smt_offset;