ionic: Keep interrupt affinity up to date
Currently the driver either sets the initial interrupt affinity for its adminq and tx/rx queues on probe or resets it on various down/up/reconfigure flows. If any user and/or user process (i.e. irqbalance) changes IRQ affinity for any of the driver's interrupts that will be reset to driver defaults whenever any down/up/reconfigure operation happens. This is incorrect and is fixed by making 2 changes: 1. Allocate an array of cpumasks that's only allocated on probe and destroyed on remove. 2. Update the cpumask(s) for interrupts that are in use by registering for affinity notifiers. Signed-off-by: Brett Creeley <brett.creeley@amd.com> Signed-off-by: Shannon Nelson <shannon.nelson@amd.com> Link: https://lore.kernel.org/r/20240619003257.6138-3-shannon.nelson@amd.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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@ -54,6 +54,7 @@ struct ionic {
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unsigned int nrxqs_per_lif;
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unsigned int nintrs;
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DECLARE_BITMAP(intrs, IONIC_INTR_CTRL_REGS_MAX);
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cpumask_var_t *affinity_masks;
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struct work_struct nb_work;
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struct notifier_block nb;
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struct rw_semaphore vf_op_lock; /* lock for VF operations */
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@ -280,9 +280,9 @@ struct ionic_intr_info {
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u64 rearm_count;
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unsigned int index;
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unsigned int vector;
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unsigned int cpu;
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u32 dim_coal_hw;
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cpumask_t affinity_mask;
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cpumask_var_t *affinity_mask;
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struct irq_affinity_notify aff_notify;
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};
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struct ionic_cq {
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@ -265,6 +265,18 @@ static void ionic_intr_free(struct ionic *ionic, int index)
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clear_bit(index, ionic->intrs);
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}
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static void ionic_irq_aff_notify(struct irq_affinity_notify *notify,
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const cpumask_t *mask)
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{
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struct ionic_intr_info *intr = container_of(notify, struct ionic_intr_info, aff_notify);
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cpumask_copy(*intr->affinity_mask, mask);
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}
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static void ionic_irq_aff_release(struct kref __always_unused *ref)
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{
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}
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static int ionic_qcq_enable(struct ionic_qcq *qcq)
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{
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struct ionic_queue *q = &qcq->q;
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@ -299,8 +311,10 @@ static int ionic_qcq_enable(struct ionic_qcq *qcq)
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if (qcq->flags & IONIC_QCQ_F_INTR) {
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napi_enable(&qcq->napi);
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irq_set_affinity_notifier(qcq->intr.vector,
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&qcq->intr.aff_notify);
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irq_set_affinity_hint(qcq->intr.vector,
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&qcq->intr.affinity_mask);
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*qcq->intr.affinity_mask);
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ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
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IONIC_INTR_MASK_CLEAR);
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}
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@ -334,6 +348,7 @@ static int ionic_qcq_disable(struct ionic_lif *lif, struct ionic_qcq *qcq, int f
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ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
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IONIC_INTR_MASK_SET);
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synchronize_irq(qcq->intr.vector);
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irq_set_affinity_notifier(qcq->intr.vector, NULL);
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irq_set_affinity_hint(qcq->intr.vector, NULL);
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napi_disable(&qcq->napi);
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}
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@ -474,6 +489,7 @@ static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq,
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static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq)
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{
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cpumask_var_t *affinity_mask;
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int err;
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if (!(qcq->flags & IONIC_QCQ_F_INTR)) {
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@ -505,10 +521,19 @@ static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qc
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}
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/* try to get the irq on the local numa node first */
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qcq->intr.cpu = cpumask_local_spread(qcq->intr.index,
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dev_to_node(lif->ionic->dev));
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if (qcq->intr.cpu != -1)
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cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask);
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affinity_mask = &lif->ionic->affinity_masks[qcq->intr.index];
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if (cpumask_empty(*affinity_mask)) {
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unsigned int cpu;
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cpu = cpumask_local_spread(qcq->intr.index,
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dev_to_node(lif->ionic->dev));
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if (cpu != -1)
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cpumask_set_cpu(cpu, *affinity_mask);
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}
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qcq->intr.affinity_mask = affinity_mask;
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qcq->intr.aff_notify.notify = ionic_irq_aff_notify;
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qcq->intr.aff_notify.release = ionic_irq_aff_release;
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netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index);
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return 0;
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@ -3120,6 +3145,44 @@ err_out:
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return err;
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}
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static int ionic_affinity_masks_alloc(struct ionic *ionic)
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{
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cpumask_var_t *affinity_masks;
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int nintrs = ionic->nintrs;
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int i;
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affinity_masks = kcalloc(nintrs, sizeof(cpumask_var_t), GFP_KERNEL);
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if (!affinity_masks)
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return -ENOMEM;
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for (i = 0; i < nintrs; i++) {
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if (!zalloc_cpumask_var_node(&affinity_masks[i], GFP_KERNEL,
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dev_to_node(ionic->dev)))
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goto err_out;
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}
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ionic->affinity_masks = affinity_masks;
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return 0;
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err_out:
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for (--i; i >= 0; i--)
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free_cpumask_var(affinity_masks[i]);
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kfree(affinity_masks);
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return -ENOMEM;
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}
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static void ionic_affinity_masks_free(struct ionic *ionic)
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{
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int i;
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for (i = 0; i < ionic->nintrs; i++)
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free_cpumask_var(ionic->affinity_masks[i]);
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kfree(ionic->affinity_masks);
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ionic->affinity_masks = NULL;
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}
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int ionic_lif_alloc(struct ionic *ionic)
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{
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struct device *dev = ionic->dev;
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@ -3211,11 +3274,15 @@ int ionic_lif_alloc(struct ionic *ionic)
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ionic_debugfs_add_lif(lif);
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err = ionic_affinity_masks_alloc(ionic);
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if (err)
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goto err_out_free_lif_info;
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/* allocate control queues and txrx queue arrays */
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ionic_lif_queue_identify(lif);
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err = ionic_qcqs_alloc(lif);
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if (err)
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goto err_out_free_lif_info;
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goto err_out_free_affinity_masks;
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/* allocate rss indirection table */
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tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
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@ -3237,6 +3304,8 @@ int ionic_lif_alloc(struct ionic *ionic)
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err_out_free_qcqs:
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ionic_qcqs_free(lif);
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err_out_free_affinity_masks:
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ionic_affinity_masks_free(lif->ionic);
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err_out_free_lif_info:
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dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
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lif->info = NULL;
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@ -3410,6 +3479,8 @@ void ionic_lif_free(struct ionic_lif *lif)
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if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
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ionic_lif_reset(lif);
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ionic_affinity_masks_free(lif->ionic);
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/* free lif info */
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kfree(lif->identity);
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dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
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@ -3487,7 +3558,7 @@ static int ionic_lif_adminq_init(struct ionic_lif *lif)
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if (qcq->flags & IONIC_QCQ_F_INTR) {
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irq_set_affinity_hint(qcq->intr.vector,
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&qcq->intr.affinity_mask);
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*qcq->intr.affinity_mask);
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ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
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IONIC_INTR_MASK_CLEAR);
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}
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