kevin/linux
1
Fork 0
Code

dt-bindings: net: xlnx,axi-ethernet: Add missing reg minItems

Browse Source 
Add missing reg minItems as based on current binding document
only ethernet MAC IO space is a supported configuration.

There is a bug in schema, current examples contain 64-bit
addressing as well as 32-bit addressing. The schema validation
does pass incidentally considering one 64-bit reg address as
two 32-bit reg address entries. If we change axi_ethernet_eth1
example node reg addressing to 32-bit schema validation reports:

Documentation/devicetree/bindings/net/xlnx,axi-ethernet.example.dtb:
ethernet@40000000: reg: [[1073741824, 262144]] is too short

To fix it add missing reg minItems constraints and to make things clearer
stick to 32-bit addressing in examples.

Fixes: cbb1ca6d5f ("dt-bindings: net: xlnx,axi-ethernet: convert bindings document to yaml")
Signed-off-by: Ravikanth Tuniki <ravikanth.tuniki@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/1727723615-2109795-1-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Ravikanth Tuniki 2024-10-01 00:43:35 +05:30 committed by Paolo Abeni
parent b63ad06ddd
commit c6929644c1
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
View File

@ -34,6 +34,7 @@ properties:
and length of the AXI DMA controller IO space, unless and length of the AXI DMA controller IO space, unless
axistream-connected is specified, in which case the reg axistream-connected is specified, in which case the reg
attribute of the node referenced by it is used. attribute of the node referenced by it is used.
minItems: 1
maxItems: 2 maxItems: 2
interrupts: interrupts:
@ -181,7 +182,7 @@ examples:
clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk"; clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>; clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
phy-mode = "mii"; phy-mode = "mii";
reg = <0x00 0x40000000 0x00 0x40000>; reg = <0x40000000 0x40000>;
xlnx,rxcsum = <0x2>; xlnx,rxcsum = <0x2>;
xlnx,rxmem = <0x800>; xlnx,rxmem = <0x800>;
xlnx,txcsum = <0x2>; xlnx,txcsum = <0x2>;