perf vendor events riscv: add Sifive U74 JSON file
This patch add the Sifive U74 JSON file. Link: https://sifive.cdn.prismic.io/sifive/ad5577a0-9a00-45c9-a5d0-424a3d586060_u74_core_complex_manual_21G3.pdf Derived-from-code-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt> Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Tested-by: Kautuk Consul <kconsul@ventanamicro.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Anup Patel <anup@brainfault.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: linux-riscv@lists.infradead.org Cc: linux@yadro.com Link: https://lore.kernel.org/r/20220815132251.25702-4-nikita.shubin@maquefel.me Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
parent
8f0dcb4e73
commit
c4f769d409
tools/perf/pmu-events/arch/riscv
17
tools/perf/pmu-events/arch/riscv/mapfile.csv
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tools/perf/pmu-events/arch/riscv/mapfile.csv
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# Format:
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# MVENDORID-MARCHID-MIMPID,Version,JSON/file/pathname,Type
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#
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# where
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# MVENDORID JEDEC code of the core provider
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# MARCHID base microarchitecture of the hart
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# MIMPID unique encoding of the version
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# of the processor implementation
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# Version could be used to track version of JSON file
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# but currently unused.
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# JSON/file/pathname is the path to JSON file, relative
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# to tools/perf/pmu-events/arch/riscv/.
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# Type is core, uncore etc
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#
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#
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#MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
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0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
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68
tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json
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tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json
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[
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{
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"ArchStdEvent": "FW_MISALIGNED_LOAD"
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},
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{
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"ArchStdEvent": "FW_MISALIGNED_STORE"
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},
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{
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"ArchStdEvent": "FW_ACCESS_LOAD"
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},
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{
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"ArchStdEvent": "FW_ACCESS_STORE"
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},
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{
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"ArchStdEvent": "FW_ILLEGAL_INSN"
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},
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{
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"ArchStdEvent": "FW_SET_TIMER"
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},
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{
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"ArchStdEvent": "FW_IPI_SENT"
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},
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{
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"ArchStdEvent": "FW_IPI_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_FENCE_I_SENT"
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},
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{
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"ArchStdEvent": "FW_FENCE_I_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_SENT"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
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}
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]
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[
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{
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"EventName": "EXCEPTION_TAKEN",
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"EventCode": "0x0000100",
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"BriefDescription": "Exception taken"
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},
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{
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"EventName": "INTEGER_LOAD_RETIRED",
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"EventCode": "0x0000200",
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"BriefDescription": "Integer load instruction retired"
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},
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{
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"EventName": "INTEGER_STORE_RETIRED",
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"EventCode": "0x0000400",
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"BriefDescription": "Integer store instruction retired"
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},
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{
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"EventName": "ATOMIC_MEMORY_RETIRED",
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"EventCode": "0x0000800",
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"BriefDescription": "Atomic memory operation retired"
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},
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{
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"EventName": "SYSTEM_INSTRUCTION_RETIRED",
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"EventCode": "0x0001000",
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"BriefDescription": "System instruction retired"
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},
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{
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"EventName": "INTEGER_ARITHMETIC_RETIRED",
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"EventCode": "0x0002000",
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"BriefDescription": "Integer arithmetic instruction retired"
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},
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{
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"EventName": "CONDITIONAL_BRANCH_RETIRED",
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"EventCode": "0x0004000",
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"BriefDescription": "Conditional branch retired"
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},
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{
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"EventName": "JAL_INSTRUCTION_RETIRED",
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"EventCode": "0x0008000",
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"BriefDescription": "JAL instruction retired"
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},
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{
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"EventName": "JALR_INSTRUCTION_RETIRED",
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"EventCode": "0x0010000",
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"BriefDescription": "JALR instruction retired"
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},
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{
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"EventName": "INTEGER_MULTIPLICATION_RETIRED",
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"EventCode": "0x0020000",
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"BriefDescription": "Integer multiplication instruction retired"
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},
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{
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"EventName": "INTEGER_DIVISION_RETIRED",
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"EventCode": "0x0040000",
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"BriefDescription": "Integer division instruction retired"
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},
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{
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"EventName": "FP_LOAD_RETIRED",
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"EventCode": "0x0080000",
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"BriefDescription": "Floating-point load instruction retired"
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},
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{
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"EventName": "FP_STORE_RETIRED",
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"EventCode": "0x0100000",
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"BriefDescription": "Floating-point store instruction retired"
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},
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{
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"EventName": "FP_ADDITION_RETIRED",
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"EventCode": "0x0200000",
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"BriefDescription": "Floating-point addition retired"
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},
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{
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"EventName": "FP_MULTIPLICATION_RETIRED",
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"EventCode": "0x0400000",
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"BriefDescription": "Floating-point multiplication retired"
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},
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{
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"EventName": "FP_FUSEDMADD_RETIRED",
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"EventCode": "0x0800000",
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"BriefDescription": "Floating-point fused multiply-add retired"
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},
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{
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"EventName": "FP_DIV_SQRT_RETIRED",
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"EventCode": "0x1000000",
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"BriefDescription": "Floating-point division or square-root retired"
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},
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{
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"EventName": "OTHER_FP_RETIRED",
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"EventCode": "0x2000000",
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"BriefDescription": "Other floating-point instruction retired"
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}
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]
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32
tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
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32
tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
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[
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{
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"EventName": "ICACHE_RETIRED",
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"EventCode": "0x0000102",
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"BriefDescription": "Instruction cache miss"
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},
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{
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"EventName": "DCACHE_MISS_MMIO_ACCESSES",
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"EventCode": "0x0000202",
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"BriefDescription": "Data cache miss or memory-mapped I/O access"
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},
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{
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"EventName": "DCACHE_WRITEBACK",
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"EventCode": "0x0000402",
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"BriefDescription": "Data cache write-back"
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},
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{
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"EventName": "INST_TLB_MISS",
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"EventCode": "0x0000802",
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"BriefDescription": "Instruction TLB miss"
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},
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{
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"EventName": "DATA_TLB_MISS",
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"EventCode": "0x0001002",
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"BriefDescription": "Data TLB miss"
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},
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{
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"EventName": "UTLB_MISS",
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"EventCode": "0x0002002",
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"BriefDescription": "UTLB miss"
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}
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]
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57
tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
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57
tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
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[
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{
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"EventName": "ADDRESSGEN_INTERLOCK",
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"EventCode": "0x0000101",
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"BriefDescription": "Address-generation interlock"
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},
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{
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"EventName": "LONGLAT_INTERLOCK",
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"EventCode": "0x0000201",
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"BriefDescription": "Long-latency interlock"
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},
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{
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"EventName": "CSR_READ_INTERLOCK",
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"EventCode": "0x0000401",
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"BriefDescription": "CSR read interlock"
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},
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{
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"EventName": "ICACHE_ITIM_BUSY",
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"EventCode": "0x0000801",
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"BriefDescription": "Instruction cache/ITIM busy"
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},
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{
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"EventName": "DCACHE_DTIM_BUSY",
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"EventCode": "0x0001001",
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"BriefDescription": "Data cache/DTIM busy"
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},
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{
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"EventName": "BRANCH_DIRECTION_MISPREDICTION",
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"EventCode": "0x0002001",
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"BriefDescription": "Branch direction misprediction"
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},
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{
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"EventName": "BRANCH_TARGET_MISPREDICTION",
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"EventCode": "0x0004001",
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"BriefDescription": "Branch/jump target misprediction"
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},
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{
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"EventName": "PIPE_FLUSH_CSR_WRITE",
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"EventCode": "0x0008001",
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"BriefDescription": "Pipeline flush from CSR write"
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},
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{
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"EventName": "PIPE_FLUSH_OTHER_EVENT",
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"EventCode": "0x0010001",
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"BriefDescription": "Pipeline flush from other event"
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},
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{
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"EventName": "INTEGER_MULTIPLICATION_INTERLOCK",
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"EventCode": "0x0020001",
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"BriefDescription": "Integer multiplication interlock"
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},
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{
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"EventName": "FP_INTERLOCK",
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"EventCode": "0x0040001",
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"BriefDescription": "Floating-point interlock"
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}
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]
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