dt-bindings: clock: Add StarFive JH7110 PLL clock generator
Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 PLL Clock Generator
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description:
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These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
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Each PLL works in integer mode or fraction mode, with configuration
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registers in the sys syscon. So the PLLs node should be a child of
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SYS-SYSCON node.
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The formula for calculating frequency is
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Fvco = Fref * (NI + NF) / M / Q1
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-pll
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clocks:
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maxItems: 1
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description: Main Oscillator (24 MHz)
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller {
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compatible = "starfive,jh7110-pll";
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clocks = <&osc>;
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#clock-cells = <1>;
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};
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#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
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#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
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/* PLL clocks */
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#define JH7110_PLLCLK_PLL0_OUT 0
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#define JH7110_PLLCLK_PLL1_OUT 1
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#define JH7110_PLLCLK_PLL2_OUT 2
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#define JH7110_PLLCLK_END 3
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/* SYSCRG clocks */
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#define JH7110_SYSCLK_CPU_ROOT 0
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#define JH7110_SYSCLK_CPU_CORE 1
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