dt-bindings: iommu: Convert msm,iommu-v0 to yaml
Convert Qualcomm IOMMU v0 implementation to yaml format. iommus part being ommited for the other bindings, as mdp4 one. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240705221520.109540-1-david@ixit.cz Signed-off-by: Will Deacon <will@kernel.org>
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David Heidelberg
Will Deacon
parent
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commit
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* QCOM IOMMU
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The MSM IOMMU is an implementation compatible with the ARM VMSA short
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descriptor page tables. It provides address translation for bus masters outside
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of the CPU, each connected to the IOMMU through a port called micro-TLB.
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Required Properties:
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- compatible: Must contain "qcom,apq8064-iommu".
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- reg: Base address and size of the IOMMU registers.
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- interrupts: Specifiers for the MMU fault interrupts. For instances that
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support secure mode two interrupts must be specified, for non-secure and
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secure mode, in that order. For instances that don't support secure mode a
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single interrupt must be specified.
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- #iommu-cells: The number of cells needed to specify the stream id. This
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is always 1.
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- qcom,ncb: The total number of context banks in the IOMMU.
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- clocks : List of clocks to be used during SMMU register access. See
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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for information about the format. For each clock specified
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here, there must be a corresponding entry in clock-names
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(see below).
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- clock-names : List of clock names corresponding to the clocks specified in
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the "clocks" property (above).
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Should be "smmu_pclk" for specifying the interface clock
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required for iommu's register accesses.
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Should be "smmu_clk" for specifying the functional clock
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required by iommu for bus accesses.
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Each bus master connected to an IOMMU must reference the IOMMU in its device
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node with the following property:
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- iommus: A reference to the IOMMU in multiple cells. The first cell is a
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phandle to the IOMMU and the second cell is the stream id.
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A single master device can be connected to more than one iommu
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and multiple contexts in each of the iommu. So multiple entries
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are required to list all the iommus and the stream ids that the
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master is connected to.
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Example: mdp iommu and its bus master
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mdp_port0: iommu@7500000 {
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compatible = "qcom,apq8064-iommu";
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#iommu-cells = <1>;
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clock-names =
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"smmu_pclk",
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"smmu_clk";
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clocks =
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<&mmcc SMMU_AHB_CLK>,
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<&mmcc MDP_AXI_CLK>;
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reg = <0x07500000 0x100000>;
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interrupts =
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<GIC_SPI 63 0>,
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<GIC_SPI 64 0>;
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qcom,ncb = <2>;
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};
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mdp: qcom,mdp@5100000 {
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compatible = "qcom,mdp";
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...
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iommus = <&mdp_port0 0
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&mdp_port0 2>;
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};
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@ -0,0 +1,78 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iommu/qcom,apq8064-iommu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm APQ8064 IOMMU
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maintainers:
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- David Heidelberg <david@ixit.cz>
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description:
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The MSM IOMMU is an implementation compatible with the ARM VMSA short
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descriptor page tables. It provides address translation for bus masters
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outside of the CPU, each connected to the IOMMU through a port called micro-TLB.
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properties:
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compatible:
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const: qcom,apq8064-iommu
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clocks:
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items:
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- description: interface clock for register accesses
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- description: functional clock for bus accesses
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clock-names:
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items:
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- const: smmu_pclk
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- const: iommu_clk
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reg:
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maxItems: 1
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interrupts:
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description: Specifiers for the MMU fault interrupts.
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minItems: 1
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items:
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- description: non-secure mode interrupt
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- description: secure mode interrupt (for instances which supports it)
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"#iommu-cells":
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const: 1
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description: Each IOMMU specifier describes a single Stream ID.
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qcom,ncb:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: The total number of context banks in the IOMMU.
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minimum: 1
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maximum: 4
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required:
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- reg
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- interrupts
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- clocks
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- clock-names
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- qcom,ncb
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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iommu@7500000 {
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compatible = "qcom,apq8064-iommu";
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reg = <0x07500000 0x100000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk SMMU_AHB_CLK>,
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<&clk MDP_AXI_CLK>;
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clock-names = "smmu_pclk",
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"iommu_clk";
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#iommu-cells = <1>;
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qcom,ncb = <2>;
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};
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