1

dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG

Document the device tree bindings for the Renesas RZ/V2H(P) SoC
Clock Pulse Generator (CPG).

CPG block handles the below operations:
- Generation and control of clock signals for the IP modules
- Generation and control of resets
- Control over booting
- Low power consumption and power supply domains

Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the
core clocks are a subset of the ones which are listed as part of section
4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240729202645.263525-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2024-07-29 21:26:43 +01:00 committed by Geert Uytterhoeven
parent 8400291e28
commit afec1aba08
2 changed files with 101 additions and 0 deletions

View File

@ -0,0 +1,80 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
and control of clock signals for the IP modules, generation and control of resets,
and control over booting, low power consumption and power supply domains.
properties:
compatible:
const: renesas,r9a09g057-cpg
reg:
maxItems: 1
clocks:
items:
- description: AUDIO_EXTAL clock input
- description: RTXIN clock input
- description: QEXTAL clock input
clock-names:
items:
- const: audio_extal
- const: rtxin
- const: qextal
'#clock-cells':
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
a module number. The module number is calculated as the CLKON register
offset index multiplied by 16, plus the actual bit in the register
used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
calculation is (1 * 16 + 3) = 0x13.
const: 2
'#power-domain-cells':
const: 0
'#reset-cells':
description:
The single reset specifier cell must be the reset number. The reset number
is calculated as the reset register offset index multiplied by 16, plus the
actual bit in the register used to reset the specific IP block. For example,
for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#power-domain-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
clock-controller@10420000 {
compatible = "renesas,r9a09g057-cpg";
reg = <0x10420000 0x10000>;
clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
clock-names = "audio_extal", "rtxin", "qextal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};

View File

@ -0,0 +1,21 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2024 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* Core Clock list */
#define R9A09G057_SYS_0_PCLK 0
#define R9A09G057_CA55_0_CORE_CLK0 1
#define R9A09G057_CA55_0_CORE_CLK1 2
#define R9A09G057_CA55_0_CORE_CLK2 3
#define R9A09G057_CA55_0_CORE_CLK3 4
#define R9A09G057_CA55_0_PERIPHCLK 5
#define R9A09G057_CM33_CLK0 6
#define R9A09G057_CST_0_SWCLKTCK 7
#define R9A09G057_IOTOP_0_SHCLK 8
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */