powerpc/8xx: Inconditionally use task PGDIR in DTLB misses
At the time being, DATA TLB miss handlers use task PGDIR for user addresses and swapper_pg_dir for kernel addresses. Now that kernel part of swapper_pg_dir is copied into task PGDIR at PGD allocation, it is possible to avoid the above logic and always use task PGDIR. But new kernel PGD entries can still be created after init, in which case those PGD entries may miss in task PGDIR. This can be handled in DATA TLB error handler. However, it needs to be done in real mode because the missing entry might be related to the stack. So implement copy of missing PGD entry in the prolog of DATA TLB ERROR handler just after the fixup of DAR. Note that this is feasible because 8xx doesn't implement vmap or ioremap with 8Mbytes pages but only 512kbytes pages which are at PTE level. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/7a76a923d2a111f1d843d8b20b4df0c65d2f4a7b.1724173828.git.christophe.leroy@csgroup.eu
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@ -40,16 +40,6 @@
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#include "head_32.h"
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.macro compare_to_kernel_boundary scratch, addr
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#if CONFIG_TASK_SIZE <= 0x80000000 && MODULES_VADDR >= 0x80000000
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/* By simply checking Address >= 0x80000000, we know if its a kernel address */
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not. \scratch, \addr
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#else
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rlwinm \scratch, \addr, 16, 0xfff8
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cmpli cr0, \scratch, TASK_SIZE@h
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#endif
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.endm
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#define PAGE_SHIFT_512K 19
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#define PAGE_SHIFT_8M 23
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@ -237,19 +227,12 @@ instruction_counter:
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START_EXCEPTION(INTERRUPT_DATA_TLB_MISS_8xx, DataStoreTLBMiss)
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mtspr SPRN_SPRG_SCRATCH2, r10
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mtspr SPRN_M_TW, r11
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mfcr r11
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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mfspr r10, SPRN_MD_EPN
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compare_to_kernel_boundary r10, r10
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mfspr r10, SPRN_M_TWB /* Get level 1 table */
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blt+ 3f
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rlwinm r10, r10, 0, 20, 31
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oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
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3:
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mtcr r11
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lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
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mtspr SPRN_MD_TWC, r11
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@ -321,15 +304,19 @@ instruction_counter:
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cmpwi cr1, r11, RPN_PATTERN
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beq- cr1, FixupDAR /* must be a buggy dcbX, icbi insn. */
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DARFixed:/* Return from dcbx instruction bug workaround */
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mfspr r11, SPRN_DSISR
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rlwinm r11, r11, 0, DSISR_NOHPTE
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cmpwi cr1, r11, 0
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beq+ cr1, .Ldtlbie
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mfspr r11, SPRN_DAR
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tlbie r11
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rlwinm r11, r11, 16, 0xffff
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cmplwi cr1, r11, TASK_SIZE@h
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bge- cr1, FixupPGD
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.Ldtlbie:
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EXCEPTION_PROLOG_1
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/* 0x300 is DataAccess exception, needed by bad_page_fault() */
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EXCEPTION_PROLOG_2 INTERRUPT_DATA_STORAGE DataTLBError handle_dar_dsisr=1
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lwz r4, _DAR(r11)
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lwz r5, _DSISR(r11)
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andis. r10,r5,DSISR_NOHPTE@h
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beq+ .Ldtlbie
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tlbie r4
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.Ldtlbie:
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prepare_transfer_to_handler
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bl do_page_fault
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b interrupt_return
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@ -383,6 +370,30 @@ DARFixed:/* Return from dcbx instruction bug workaround */
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__HEAD
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. = 0x2000
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FixupPGD:
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mtspr SPRN_M_TW, r10
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mfspr r10, SPRN_DAR
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mtspr SPRN_MD_EPN, r10
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mfspr r11, SPRN_M_TWB /* Get level 1 table */
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lwz r10, (swapper_pg_dir - PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
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cmpwi cr1, r10, 0
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bne cr1, 1f
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rlwinm r10, r11, 0, 20, 31
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oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
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lwz r10, (swapper_pg_dir - PAGE_OFFSET)@l(r10) /* Get the level 1 entry */
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cmpwi cr1, r10, 0
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beq cr1, 1f
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stw r10, (swapper_pg_dir - PAGE_OFFSET)@l(r11) /* Set the level 1 entry */
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mfspr r10, SPRN_M_TW
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mtcr r10
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mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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rfi
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1:
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mfspr r10, SPRN_M_TW
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b .Ldtlbie
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/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
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* by decoding the registers used by the dcbx instruction and adding them.
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* DAR is set to the calculated address.
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