accel/qaic: Add MHI controller
An AIC100 device contains a MHI interface with a number of different channels for controlling different aspects of the device. The MHI controller works with the MHI bus to enable and drive that interface. AIC100 uses the BHI protocol in PBL to load SBL. The MHI controller expects the SBL to be located at /lib/firmware/qcom/aic100/sbl.bin and expects the MHI bus to manage the process of loading and sending SBL to the device. Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Acked-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1679932497-30277-4-git-send-email-quic_jhugo@quicinc.com
This commit is contained in:
Jeffrey Hugo
Jacek Lawrynowicz
parent
c501ca23a6
commit
a36bf7af86
563
drivers/accel/qaic/mhi_controller.c
Normal file
563
drivers/accel/qaic/mhi_controller.c
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@ -0,0 +1,563 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */
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/* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/memblock.h>
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#include <linux/mhi.h>
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#include <linux/moduleparam.h>
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#include <linux/pci.h>
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#include <linux/sizes.h>
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#include "mhi_controller.h"
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#include "qaic.h"
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#define MAX_RESET_TIME_SEC 25
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static unsigned int mhi_timeout_ms = 2000; /* 2 sec default */
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module_param(mhi_timeout_ms, uint, 0600);
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MODULE_PARM_DESC(mhi_timeout_ms, "MHI controller timeout value");
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static struct mhi_channel_config aic100_channels[] = {
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{
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.name = "QAIC_LOOPBACK",
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.num = 0,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_TO_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_LOOPBACK",
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.num = 1,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_SAHARA",
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.num = 2,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_TO_DEVICE,
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.ee_mask = MHI_CH_EE_SBL,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_SAHARA",
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.num = 3,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = MHI_CH_EE_SBL,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_DIAG",
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.num = 4,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_TO_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_DIAG",
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.num = 5,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_SSR",
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.num = 6,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_TO_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_SSR",
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.num = 7,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_QDSS",
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.num = 8,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_TO_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_QDSS",
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.num = 9,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_CONTROL",
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.num = 10,
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.num_elements = 128,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_TO_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_CONTROL",
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.num = 11,
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.num_elements = 128,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_LOGGING",
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.num = 12,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_TO_DEVICE,
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.ee_mask = MHI_CH_EE_SBL,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_LOGGING",
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.num = 13,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = MHI_CH_EE_SBL,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_STATUS",
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.num = 14,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_TO_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_STATUS",
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.num = 15,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_TELEMETRY",
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.num = 16,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_TO_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_TELEMETRY",
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.num = 17,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_DEBUG",
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.num = 18,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_TO_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_DEBUG",
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.num = 19,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.name = "QAIC_TIMESYNC",
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.num = 20,
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_TO_DEVICE,
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.ee_mask = MHI_CH_EE_SBL | MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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{
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.num = 21,
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.name = "QAIC_TIMESYNC",
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.num_elements = 32,
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.local_elements = 0,
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.event_ring = 0,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = MHI_CH_EE_SBL | MHI_CH_EE_AMSS,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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.wake_capable = false,
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},
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};
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static struct mhi_event_config aic100_events[] = {
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{
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.num_elements = 32,
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.irq_moderation_ms = 0,
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.irq = 0,
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.channel = U32_MAX,
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.priority = 1,
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.mode = MHI_DB_BRST_DISABLE,
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.data_type = MHI_ER_CTRL,
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.hardware_event = false,
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.client_managed = false,
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.offload_channel = false,
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},
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};
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static struct mhi_controller_config aic100_config = {
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.max_channels = 128,
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.timeout_ms = 0, /* controlled by mhi_timeout */
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.buf_len = 0,
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.num_channels = ARRAY_SIZE(aic100_channels),
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.ch_cfg = aic100_channels,
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.num_events = ARRAY_SIZE(aic100_events),
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.event_cfg = aic100_events,
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.use_bounce_buf = false,
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.m2_no_db = false,
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};
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static int mhi_read_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 *out)
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{
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u32 tmp = readl_relaxed(addr);
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if (tmp == U32_MAX)
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return -EIO;
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*out = tmp;
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return 0;
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}
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static void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 val)
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{
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writel_relaxed(val, addr);
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}
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static int mhi_runtime_get(struct mhi_controller *mhi_cntrl)
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{
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return 0;
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}
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static void mhi_runtime_put(struct mhi_controller *mhi_cntrl)
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{
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}
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static void mhi_status_cb(struct mhi_controller *mhi_cntrl, enum mhi_callback reason)
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{
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struct qaic_device *qdev = pci_get_drvdata(to_pci_dev(mhi_cntrl->cntrl_dev));
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/* this event occurs in atomic context */
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if (reason == MHI_CB_FATAL_ERROR)
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pci_err(qdev->pdev, "Fatal error received from device. Attempting to recover\n");
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/* this event occurs in non-atomic context */
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if (reason == MHI_CB_SYS_ERROR)
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qaic_dev_reset_clean_local_state(qdev, true);
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}
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static int mhi_reset_and_async_power_up(struct mhi_controller *mhi_cntrl)
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{
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u8 time_sec = 1;
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int current_ee;
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int ret;
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/* Reset the device to bring the device in PBL EE */
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mhi_soc_reset(mhi_cntrl);
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/*
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* Keep checking the execution environment(EE) after every 1 second
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* interval.
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*/
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do {
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msleep(1000);
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current_ee = mhi_get_exec_env(mhi_cntrl);
|
||||
} while (current_ee != MHI_EE_PBL && time_sec++ <= MAX_RESET_TIME_SEC);
|
||||
|
||||
/* If the device is in PBL EE retry power up */
|
||||
if (current_ee == MHI_EE_PBL)
|
||||
ret = mhi_async_power_up(mhi_cntrl);
|
||||
else
|
||||
ret = -EIO;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct mhi_controller *qaic_mhi_register_controller(struct pci_dev *pci_dev, void __iomem *mhi_bar,
|
||||
int mhi_irq)
|
||||
{
|
||||
struct mhi_controller *mhi_cntrl;
|
||||
int ret;
|
||||
|
||||
mhi_cntrl = devm_kzalloc(&pci_dev->dev, sizeof(*mhi_cntrl), GFP_KERNEL);
|
||||
if (!mhi_cntrl)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
mhi_cntrl->cntrl_dev = &pci_dev->dev;
|
||||
|
||||
/*
|
||||
* Covers the entire possible physical ram region. Remote side is
|
||||
* going to calculate a size of this range, so subtract 1 to prevent
|
||||
* rollover.
|
||||
*/
|
||||
mhi_cntrl->iova_start = 0;
|
||||
mhi_cntrl->iova_stop = PHYS_ADDR_MAX - 1;
|
||||
mhi_cntrl->status_cb = mhi_status_cb;
|
||||
mhi_cntrl->runtime_get = mhi_runtime_get;
|
||||
mhi_cntrl->runtime_put = mhi_runtime_put;
|
||||
mhi_cntrl->read_reg = mhi_read_reg;
|
||||
mhi_cntrl->write_reg = mhi_write_reg;
|
||||
mhi_cntrl->regs = mhi_bar;
|
||||
mhi_cntrl->reg_len = SZ_4K;
|
||||
mhi_cntrl->nr_irqs = 1;
|
||||
mhi_cntrl->irq = devm_kmalloc(&pci_dev->dev, sizeof(*mhi_cntrl->irq), GFP_KERNEL);
|
||||
|
||||
if (!mhi_cntrl->irq)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
mhi_cntrl->irq[0] = mhi_irq;
|
||||
mhi_cntrl->fw_image = "qcom/aic100/sbl.bin";
|
||||
|
||||
/* use latest configured timeout */
|
||||
aic100_config.timeout_ms = mhi_timeout_ms;
|
||||
ret = mhi_register_controller(mhi_cntrl, &aic100_config);
|
||||
if (ret) {
|
||||
pci_err(pci_dev, "mhi_register_controller failed %d\n", ret);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
ret = mhi_prepare_for_power_up(mhi_cntrl);
|
||||
if (ret) {
|
||||
pci_err(pci_dev, "mhi_prepare_for_power_up failed %d\n", ret);
|
||||
goto prepare_power_up_fail;
|
||||
}
|
||||
|
||||
ret = mhi_async_power_up(mhi_cntrl);
|
||||
/*
|
||||
* If EIO is returned it is possible that device is in SBL EE, which is
|
||||
* undesired. SOC reset the device and try to power up again.
|
||||
*/
|
||||
if (ret == -EIO && MHI_EE_SBL == mhi_get_exec_env(mhi_cntrl)) {
|
||||
pci_err(pci_dev, "Found device in SBL at MHI init. Attempting a reset.\n");
|
||||
ret = mhi_reset_and_async_power_up(mhi_cntrl);
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
pci_err(pci_dev, "mhi_async_power_up failed %d\n", ret);
|
||||
goto power_up_fail;
|
||||
}
|
||||
|
||||
return mhi_cntrl;
|
||||
|
||||
power_up_fail:
|
||||
mhi_unprepare_after_power_down(mhi_cntrl);
|
||||
prepare_power_up_fail:
|
||||
mhi_unregister_controller(mhi_cntrl);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
void qaic_mhi_free_controller(struct mhi_controller *mhi_cntrl, bool link_up)
|
||||
{
|
||||
mhi_power_down(mhi_cntrl, link_up);
|
||||
mhi_unprepare_after_power_down(mhi_cntrl);
|
||||
mhi_unregister_controller(mhi_cntrl);
|
||||
}
|
||||
|
||||
void qaic_mhi_start_reset(struct mhi_controller *mhi_cntrl)
|
||||
{
|
||||
mhi_power_down(mhi_cntrl, true);
|
||||
}
|
||||
|
||||
void qaic_mhi_reset_done(struct mhi_controller *mhi_cntrl)
|
||||
{
|
||||
struct pci_dev *pci_dev = container_of(mhi_cntrl->cntrl_dev, struct pci_dev, dev);
|
||||
int ret;
|
||||
|
||||
ret = mhi_async_power_up(mhi_cntrl);
|
||||
if (ret)
|
||||
pci_err(pci_dev, "mhi_async_power_up failed after reset %d\n", ret);
|
||||
}
|
||||
16
drivers/accel/qaic/mhi_controller.h
Normal file
16
drivers/accel/qaic/mhi_controller.h
Normal file
@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef MHICONTROLLERQAIC_H_
|
||||
#define MHICONTROLLERQAIC_H_
|
||||
|
||||
struct mhi_controller *qaic_mhi_register_controller(struct pci_dev *pci_dev, void __iomem *mhi_bar,
|
||||
int mhi_irq);
|
||||
void qaic_mhi_free_controller(struct mhi_controller *mhi_cntrl, bool link_up);
|
||||
void qaic_mhi_start_reset(struct mhi_controller *mhi_cntrl);
|
||||
void qaic_mhi_reset_done(struct mhi_controller *mhi_cntrl);
|
||||
|
||||
#endif /* MHICONTROLLERQAIC_H_ */
|
||||
Loading…
Reference in New Issue
Block a user